文件名称:Center

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 849kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 刘**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

使用Xilinx3S400开发的钢板检测算法中心化算法,通过测试。-a vhdl-program use Xilinx3S400
相关搜索: AT91SAM9263_SRC_v100

(系统自动生成,下载前可以参看下载内容)

下载文件列表

Center

......\Center.bld

......\Center.cmd_log

......\Center.ise

......\Center.ise_ISE_Backup

......\Center.lso

......\Center.ngc

......\Center.ngd

......\Center.ngr

......\Center.ntrc_log

......\Center.pcf

......\Center.prj

......\Center.stx

......\Center.syr

......\Center.vhd

......\Center.xst

......\Center_map.map

......\Center_map.mrp

......\Center_map.ncd

......\Center_map.ngm

......\Center_prev_built.ngd

......\Center_summary.html

......\Center_summary.xml

......\Center_usage.xml

......\Center_vhdl.prj

......\modelsim.ini

......\netgen

......\......\map

......\......\...\Center_map.nlf

......\......\...\Center_map.sdf

......\......\...\Center_map.vhd

......\Ram.asy

......\Ram.mif

......\Ram.ngc

......\Ram.sym

......\Ram.v

......\Ram.veo

......\Ram.vhd

......\Ram.vho

......\Ram.xco

......\Ram_flist.txt

......\Ram_readme.txt

......\Ram_summary.html

......\Ram_xmdf.tcl

......\rom100.coe

......\rom_12.coe

......\rom_13.coe

......\tb_center.vhd

......\tb_center_vhd.mdo

......\tb_center_vhd.udo

......\templates

......\.........\coregen.xml

......\tmp

......\...\_cg

......\top.cmd_log

......\top.lso

......\top.prj

......\top.syr

......\top.xst

......\top_summary.html

......\top_vhdl.prj

......\transcript

......\vsim.wlf

......\work

......\....\center

......\....\......\structure.dat

......\....\......\_primary.dat

......\....\tb_center_vhd

......\....\.............\behavior.dat

......\....\.............\_primary.dat

......\....\_info

......\....\_opt

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vcomponents__vhdl.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vpackage_body.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vpackage__vhdl.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_and2_x_and2_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_bufgmux_x_bufgmux_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_buf_x_buf_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_ff_x_ff_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_inv_x_inv_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_lut4_x_lut4_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_mult18x18_x_mult18x18_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_mux2_x_mux2_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_mux2_x_mux2_v__2.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_obuf_x_obuf_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_one_x_one_v.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_ramb16_s2_x_ramb16_s2_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_roc_x_roc_v.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_sff_x_sff_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_toc_x_toc_v.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_xor2_x_xor2_v__1.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_zero_x_zero_v.asm

......\....\....\D__FPGA_ModelSim_xilinx_lib_simprim__info

......\....\....\work_center_structure__1.asm

......\....\....\work_tb_center_vhd_behavior__1.asm

......\....\....\work__info

......\....\....\_deps

......\....\....\__model_tech_.._ieee__info

......\....\....\__model_tech_.._std__info

......\....\....\__model_tech_.._vital2000__info

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