文件名称:GBJC
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平坦度检测中的高度检测算法，使用ISE开发环境，语言为VHDL，平台是XC3S4-a vhdl_program used for flat detect
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下载文件列表
GBJC
....\Center.bld
....\Center.cmd_log
....\Center.lso
....\Center.ngc
....\Center.ngd
....\Center.ngr
....\Center.pcf
....\Center.prj
....\Center.spl
....\Center.stx
....\Center.sym
....\Center.syr
....\Center.vhd
....\Center.xst
....\Center_map.map
....\Center_map.mrp
....\Center_map.ncd
....\Center_map.ngm
....\Center_prev_built.ngd
....\Center_summary.xml
....\Center_usage.xml
....\Center_vhdl.prj
....\choose.vhd
....\GBJC.ise
....\GBJC.ise_ISE_Backup
....\GBJC.ntrc_log
....\modelsim.ini
....\netgen
....\......\map
....\......\...\Center_map.nlf
....\......\...\Center_map.sdf
....\......\...\Center_map.vhd
....\......\translate
....\......\.........\Center_translate.nlf
....\......\.........\Center_translate.vhd
....\pepExtractor.prj
....\Ram1.asy
....\Ram1.mif
....\Ram1.ngc
....\Ram1.sym
....\Ram1.v
....\Ram1.veo
....\Ram1.vhd
....\Ram1.vho
....\Ram1.xco
....\Ram1_flist.txt
....\Ram1_readme.txt
....\Ram1_xmdf.tcl
....\Ram2.asy
....\Ram2.mif
....\Ram2.ngc
....\Ram2.sym
....\Ram2.v
....\Ram2.veo
....\Ram2.vhd
....\Ram2.vho
....\Ram2.xco
....\Ram2_flist.txt
....\Ram2_readme.txt
....\Ram2_xmdf.tcl
....\rom1.coe
....\rom1.coe.bak
....\rom2.coe
....\rom2.coe.bak
....\rom_1.coe
....\rom_11.coe
....\rom_11.txt.bak
....\rom_12.coe
....\rom_2.coe
....\select.vhd
....\tb_center.vhd
....\tb_center_vhd.mdo
....\tb_center_vhd.udo
....\tb_counter.vhd
....\tb_counter_vhd.mdo
....\tb_counter_vhd.ndo
....\tb_counter_vhd.udo
....\templates
....\.........\coregen.xml
....\tmp
....\...\_cg
....\transcript
....\vsim.wlf
....\work
....\....\center
....\....\......\structure.dat
....\....\......\_primary.dat
....\....\tb_counter_vhd
....\....\..............\behavior.dat
....\....\..............\_primary.dat
....\....\_info
....\....\_opt
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vcomponents__vhdl.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vpackage_body.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vpackage__vhdl.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_and2_x_and2_v__1.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_bufgmux_x_bufgmux_v__1.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_buf_x_buf_v__1.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_ff_x_ff_v__1.asm
....\Center.bld
....\Center.cmd_log
....\Center.lso
....\Center.ngc
....\Center.ngd
....\Center.ngr
....\Center.pcf
....\Center.prj
....\Center.spl
....\Center.stx
....\Center.sym
....\Center.syr
....\Center.vhd
....\Center.xst
....\Center_map.map
....\Center_map.mrp
....\Center_map.ncd
....\Center_map.ngm
....\Center_prev_built.ngd
....\Center_summary.xml
....\Center_usage.xml
....\Center_vhdl.prj
....\choose.vhd
....\GBJC.ise
....\GBJC.ise_ISE_Backup
....\GBJC.ntrc_log
....\modelsim.ini
....\netgen
....\......\map
....\......\...\Center_map.nlf
....\......\...\Center_map.sdf
....\......\...\Center_map.vhd
....\......\translate
....\......\.........\Center_translate.nlf
....\......\.........\Center_translate.vhd
....\pepExtractor.prj
....\Ram1.asy
....\Ram1.mif
....\Ram1.ngc
....\Ram1.sym
....\Ram1.v
....\Ram1.veo
....\Ram1.vhd
....\Ram1.vho
....\Ram1.xco
....\Ram1_flist.txt
....\Ram1_readme.txt
....\Ram1_xmdf.tcl
....\Ram2.asy
....\Ram2.mif
....\Ram2.ngc
....\Ram2.sym
....\Ram2.v
....\Ram2.veo
....\Ram2.vhd
....\Ram2.vho
....\Ram2.xco
....\Ram2_flist.txt
....\Ram2_readme.txt
....\Ram2_xmdf.tcl
....\rom1.coe
....\rom1.coe.bak
....\rom2.coe
....\rom2.coe.bak
....\rom_1.coe
....\rom_11.coe
....\rom_11.txt.bak
....\rom_12.coe
....\rom_2.coe
....\select.vhd
....\tb_center.vhd
....\tb_center_vhd.mdo
....\tb_center_vhd.udo
....\tb_counter.vhd
....\tb_counter_vhd.mdo
....\tb_counter_vhd.ndo
....\tb_counter_vhd.udo
....\templates
....\.........\coregen.xml
....\tmp
....\...\_cg
....\transcript
....\vsim.wlf
....\work
....\....\center
....\....\......\structure.dat
....\....\......\_primary.dat
....\....\tb_counter_vhd
....\....\..............\behavior.dat
....\....\..............\_primary.dat
....\....\_info
....\....\_opt
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vcomponents__vhdl.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vpackage_body.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_vpackage__vhdl.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_and2_x_and2_v__1.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_bufgmux_x_bufgmux_v__1.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_buf_x_buf_v__1.asm
....\....\....\D__FPGA_ModelSim_xilinx_lib_simprim_x_ff_x_ff_v__1.asm