文件名称:CORE8051_ADC_OK_328
介绍说明－－下载内容均来自于网络，请自行研究使用
这是一个在Fusion系列的AFS600的FPGA，在里面嵌入51核和12位adc模块，可以在lcd12864上显示，能正常转换电压。做adc使用。-This is a AFS600 at the Fusion series FPGA, embedded in which 51 nuclear and 12-bit adc module, you can show up at lcd12864 to the normal voltage conversion. Does the use of adc.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
CORE8051_ADC_OK_328
...................\3.28.txt
...................\cnt.v
...................\component
...................\constraint
...................\..........\TOP_CORE8051_sdc.sdc
...................\core8051.hex
...................\CORE8051_ROM_OK.prj
...................\coreconsole
...................\designer
...................\........\impl1
...................\........\.....\ada00224-1.tmp
...................\........\.....\designer.log
...................\........\.....\designer_genhdl.log
...................\........\.....\sdcrd.log
...................\........\.....\simulation
...................\........\.....\..........\postlayout
...................\........\.....\..........\..........\@t@o@p_@f@p@g@a
...................\........\.....\..........\..........\...............\verilog.psm
...................\........\.....\..........\..........\...............\_primary.dat
...................\........\.....\..........\..........\...............\_primary.dbs
...................\........\.....\..........\..........\...............\_primary.vhd
...................\........\.....\..........\..........\stimulus
...................\........\.....\..........\..........\........\verilog.psm
...................\........\.....\..........\..........\........\_primary.dat
...................\........\.....\..........\..........\........\_primary.dbs
...................\........\.....\..........\..........\........\_primary.vhd
...................\........\.....\..........\..........\tb_clock_minmax
...................\........\.....\..........\..........\...............\verilog.psm
...................\........\.....\..........\..........\...............\_primary.dat
...................\........\.....\..........\..........\...............\_primary.dbs
...................\........\.....\..........\..........\...............\_primary.vhd
...................\........\.....\..........\..........\_info
...................\........\.....\..........\..........\_temp
...................\........\.....\TOP_CORE8051.adb
...................\........\.....\TOP_CORE8051.dtf
...................\........\.....\................\verify.log
...................\........\.....\TOP_CORE8051.ide_des
...................\........\.....\TOP_CORE8051.pdb
...................\........\.....\TOP_CORE8051.pdb.depends
...................\........\.....\TOP_CORE8051.tcl
...................\........\.....\TOP_CORE8051_1.adb
...................\........\.....\TOP_CORE8051_1.dtf
...................\........\.....\..................\verify.log
...................\........\.....\TOP_CORE8051_1.ide_des
...................\........\.....\TOP_CORE8051_1.pdb
...................\........\.....\TOP_CORE8051_1.pdb.depends
...................\........\.....\TOP_CORE8051_1_ba.sdf
...................\........\.....\TOP_CORE8051_1_ba.v
...................\........\.....\TOP_CORE8051_ba.sdf
...................\........\.....\TOP_CORE8051_ba.v
...................\........\.....\TOP_CORE8051_fp
...................\........\.....\...............\$$FlashPro_FPBBALTLPT1.L$$
...................\........\.....\...............\projectData
...................\........\.....\...............\...........\TOP_CORE8051.pdb
...................\........\.....\...............\TOP_CORE8051.log
...................\........\.....\...............\TOP_CORE8051.pro
...................\........\.....\TOP_FPGA.adb
...................\........\.....\TOP_FPGA.dtf
...................\........\.....\............\verify.log
...................\........\.....\TOP_FPGA.ide_des
...................\........\.....\TOP_FPGA.pdb
...................\........\.....\TOP_FPGA.pdb.depends
...................\........\.....\TOP_FPGA.plk
...................\........\.....\TOP_FPGA.tcl
...................\........\.....\TOP_FPGA_ba.sdf
...................\........\.....\TOP_FPGA_ba.v
...................\........\.....\TOP_FPGA_fp
...................\........\.....\...........\$$FlashPro_FPBBALTLPT1.L$$
...................\........\.....\...........\projectData
...................\........\.....\...........\...
...................\3.28.txt
...................\cnt.v
...................\component
...................\constraint
...................\..........\TOP_CORE8051_sdc.sdc
...................\core8051.hex
...................\CORE8051_ROM_OK.prj
...................\coreconsole
...................\designer
...................\........\impl1
...................\........\.....\ada00224-1.tmp
...................\........\.....\designer.log
...................\........\.....\designer_genhdl.log
...................\........\.....\sdcrd.log
...................\........\.....\simulation
...................\........\.....\..........\postlayout
...................\........\.....\..........\..........\@t@o@p_@f@p@g@a
...................\........\.....\..........\..........\...............\verilog.psm
...................\........\.....\..........\..........\...............\_primary.dat
...................\........\.....\..........\..........\...............\_primary.dbs
...................\........\.....\..........\..........\...............\_primary.vhd
...................\........\.....\..........\..........\stimulus
...................\........\.....\..........\..........\........\verilog.psm
...................\........\.....\..........\..........\........\_primary.dat
...................\........\.....\..........\..........\........\_primary.dbs
...................\........\.....\..........\..........\........\_primary.vhd
...................\........\.....\..........\..........\tb_clock_minmax
...................\........\.....\..........\..........\...............\verilog.psm
...................\........\.....\..........\..........\...............\_primary.dat
...................\........\.....\..........\..........\...............\_primary.dbs
...................\........\.....\..........\..........\...............\_primary.vhd
...................\........\.....\..........\..........\_info
...................\........\.....\..........\..........\_temp
...................\........\.....\TOP_CORE8051.adb
...................\........\.....\TOP_CORE8051.dtf
...................\........\.....\................\verify.log
...................\........\.....\TOP_CORE8051.ide_des
...................\........\.....\TOP_CORE8051.pdb
...................\........\.....\TOP_CORE8051.pdb.depends
...................\........\.....\TOP_CORE8051.tcl
...................\........\.....\TOP_CORE8051_1.adb
...................\........\.....\TOP_CORE8051_1.dtf
...................\........\.....\..................\verify.log
...................\........\.....\TOP_CORE8051_1.ide_des
...................\........\.....\TOP_CORE8051_1.pdb
...................\........\.....\TOP_CORE8051_1.pdb.depends
...................\........\.....\TOP_CORE8051_1_ba.sdf
...................\........\.....\TOP_CORE8051_1_ba.v
...................\........\.....\TOP_CORE8051_ba.sdf
...................\........\.....\TOP_CORE8051_ba.v
...................\........\.....\TOP_CORE8051_fp
...................\........\.....\...............\$$FlashPro_FPBBALTLPT1.L$$
...................\........\.....\...............\projectData
...................\........\.....\...............\...........\TOP_CORE8051.pdb
...................\........\.....\...............\TOP_CORE8051.log
...................\........\.....\...............\TOP_CORE8051.pro
...................\........\.....\TOP_FPGA.adb
...................\........\.....\TOP_FPGA.dtf
...................\........\.....\............\verify.log
...................\........\.....\TOP_FPGA.ide_des
...................\........\.....\TOP_FPGA.pdb
...................\........\.....\TOP_FPGA.pdb.depends
...................\........\.....\TOP_FPGA.plk
...................\........\.....\TOP_FPGA.tcl
...................\........\.....\TOP_FPGA_ba.sdf
...................\........\.....\TOP_FPGA_ba.v
...................\........\.....\TOP_FPGA_fp
...................\........\.....\...........\$$FlashPro_FPBBALTLPT1.L$$
...................\........\.....\...........\projectData
...................\........\.....\...........\...