文件名称:Uartmodule
介绍说明－－下载内容均来自于网络，请自行研究使用
实现FPGA与PC机的串口通信功能，实现数据的收发。-FPGA with the realization of PC-serial communication functions to send and receive data.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Uartmodule
..........\stdout.log
..........\tp.v
..........\uart_module.cr.mti
..........\uart_module.mpf
..........\Uart_rx.v
..........\Uart_test.v
..........\Uart_test.v.bak
..........\uart_top.v
..........\uart_top.v.bak
..........\Uart_tx.v
..........\vish_stacktrace.vstf
..........\vsim.wlf
..........\work
..........\....\@uart_test
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\uart
..........\....\....\verilog.asm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\uart_rx
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\uart_tx
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\_info
..........\stdout.log
..........\tp.v
..........\uart_module.cr.mti
..........\uart_module.mpf
..........\Uart_rx.v
..........\Uart_test.v
..........\Uart_test.v.bak
..........\uart_top.v
..........\uart_top.v.bak
..........\Uart_tx.v
..........\vish_stacktrace.vstf
..........\vsim.wlf
..........\work
..........\....\@uart_test
..........\....\..........\verilog.asm
..........\....\..........\_primary.dat
..........\....\..........\_primary.vhd
..........\....\uart
..........\....\....\verilog.asm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\uart_rx
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\uart_tx
..........\....\.......\verilog.asm
..........\....\.......\_primary.dat
..........\....\.......\_primary.vhd
..........\....\_info