文件名称:RiscCpu
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Verilog-RISC CPU 代码
实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。
北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted ModelSim simulation. BUAA
实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。
北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware descr iption language, and design methods. The procedure adopted ModelSim simulation. BUAA
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RiscCpu
.......\accum.v
.......\addr_decode.v
.......\adr.v
.......\alu.v
.......\clk_gen.v
.......\counter.v
.......\cpu.v
.......\cputop.v
.......\datactl.v
.......\machine.v
.......\machinectl.v
.......\ram.v
.......\register.v
.......\rom.v
.......\test1.dat
.......\test1.pro
.......\test2.dat
.......\test2.pro
.......\test3.dat
.......\test3.pro
.......\transcript
.......\accum.v
.......\addr_decode.v
.......\adr.v
.......\alu.v
.......\clk_gen.v
.......\counter.v
.......\cpu.v
.......\cputop.v
.......\datactl.v
.......\machine.v
.......\machinectl.v
.......\ram.v
.......\register.v
.......\rom.v
.......\test1.dat
.......\test1.pro
.......\test2.dat
.......\test2.pro
.......\test3.dat
.......\test3.pro
.......\transcript