文件名称:an501_design_example
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PWM文件
用于CPLD，学习如何用VHDL语言写程序-PWM files for CPLD, learn how to write VHDL language program
用于CPLD，学习如何用VHDL语言写程序-PWM files for CPLD, learn how to write VHDL language program
(系统自动生成,下载前可以参看下载内容)
下载文件列表
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example
.............................................................\code
.............................................................\....\pwm_main.v
.............................................................\modelsim
.............................................................\........\pulse_width_modulator.cr.mti
.............................................................\........\pulse_width_modulator.mpf
.............................................................\........\pwm_main.v
.............................................................\........\pwm_sim.cr.mti
.............................................................\........\pwm_sim.mpf
.............................................................\........\test_pwm.v
.............................................................\........\wave.do
.............................................................\........\wave2.do
.............................................................\........\wave3.do
.............................................................\........\wave4.do
.............................................................\........\wave5.do
.............................................................\........\work
.............................................................\........\....\altufm_osc0_altufm_osc_1p3
.............................................................\........\....\..........................\verilog.asm
.............................................................\........\....\..........................\_primary.dat
.............................................................\........\....\..........................\_primary.vhd
.............................................................\........\....\clkgen
.............................................................\........\....\......\verilog.asm
.............................................................\........\....\......\_primary.dat
.............................................................\........\....\......\_primary.vhd
.............................................................\........\....\clk_gen
.............................................................\........\....\.......\verilog.asm
.............................................................\........\....\.......\_primary.dat
.............................................................\........\....\.......\_primary.vhd
.............................................................\........\....\dutycycle
.............................................................\........\....\.........\verilog.asm
.............................................................\........\....\.........\_primary.dat
.............................................................\........\....\.........\_primary.vhd
.............................................................\........\....\duty_cycle
.............................................................\........\....\..........\verilog.asm
.............................................................\........\....\..........\_primary.dat
.............................................................\........\....\..........\_primary.vhd
.............................................................\........\....\pwm_gen
.............................................................\........\....\.......\verilog.asm
.............................................................\........\....\.......\_primary.dat
.............................................................\........\....\.......\_primary.vhd
.............................................................\........\....\pwm_main
.............................................................\........\....\........\verilog.asm
.............................................................\........\....\........\_primary.dat
.............................................................\........\....\........\_primary.vhd
.............................................................\........\....\test_pwm
.........
.............................................................\code
.............................................................\....\pwm_main.v
.............................................................\modelsim
.............................................................\........\pulse_width_modulator.cr.mti
.............................................................\........\pulse_width_modulator.mpf
.............................................................\........\pwm_main.v
.............................................................\........\pwm_sim.cr.mti
.............................................................\........\pwm_sim.mpf
.............................................................\........\test_pwm.v
.............................................................\........\wave.do
.............................................................\........\wave2.do
.............................................................\........\wave3.do
.............................................................\........\wave4.do
.............................................................\........\wave5.do
.............................................................\........\work
.............................................................\........\....\altufm_osc0_altufm_osc_1p3
.............................................................\........\....\..........................\verilog.asm
.............................................................\........\....\..........................\_primary.dat
.............................................................\........\....\..........................\_primary.vhd
.............................................................\........\....\clkgen
.............................................................\........\....\......\verilog.asm
.............................................................\........\....\......\_primary.dat
.............................................................\........\....\......\_primary.vhd
.............................................................\........\....\clk_gen
.............................................................\........\....\.......\verilog.asm
.............................................................\........\....\.......\_primary.dat
.............................................................\........\....\.......\_primary.vhd
.............................................................\........\....\dutycycle
.............................................................\........\....\.........\verilog.asm
.............................................................\........\....\.........\_primary.dat
.............................................................\........\....\.........\_primary.vhd
.............................................................\........\....\duty_cycle
.............................................................\........\....\..........\verilog.asm
.............................................................\........\....\..........\_primary.dat
.............................................................\........\....\..........\_primary.vhd
.............................................................\........\....\pwm_gen
.............................................................\........\....\.......\verilog.asm
.............................................................\........\....\.......\_primary.dat
.............................................................\........\....\.......\_primary.vhd
.............................................................\........\....\pwm_main
.............................................................\........\....\........\verilog.asm
.............................................................\........\....\........\_primary.dat
.............................................................\........\....\........\_primary.vhd
.............................................................\........\....\test_pwm
.........