文件名称:YDFPGA
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基础性试验
实践性试验
综合性试验
提升性试验
交通灯设计-The basis of practical test test test integrated testing to enhance the design of traffic lights
实践性试验
综合性试验
提升性试验
交通灯设计-The basis of practical test test test integrated testing to enhance the design of traffic lights
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下载文件列表
FPGA实验仪用户指南.pdf
交通灯的设计
............\VHDL程序
............\........\dynamic_display.vhd
............\........\state_machine.vhd
............\........\top_traffic_light1.vhd
............\........\yellowflash.vhd
............\下载文件
............\........\top_traffic_light1.bit
............\锁脚文件
............\........\top_traffic.ucf
基础性试验
..........\交通灯的设计
..........\............\VHDL程序
..........\............\........\dynamic_display.vhd
..........\............\........\state_machine.vhd
..........\............\........\top_traffic_light1.vhd
..........\............\........\yellowflash.vhd
..........\............\下载文件
..........\............\........\top_traffic_light1.bit
..........\............\锁脚文件
..........\............\........\top_traffic.ucf
..........\基础试验
..........\........\LED显示试验
..........\........\...........\VHDL文件
..........\........\...........\........\led.vhd
..........\........\...........\下载文件
..........\........\...........\........\led.bit
..........\........\...........\........\led_cclktemp.bit
..........\........\...........\锁脚文件
..........\........\...........\........\led.ucf
..........\........\按键防抖动
..........\........\..........\VHDL文件
..........\........\..........\........\button_test.vhd
..........\........\..........\下载文件
..........\........\..........\........\button_test.bit
..........\........\..........\锁脚文件
..........\........\..........\........\button_test.ucf
..........\........\数值比较器
..........\........\..........\VHDL文件
..........\........\..........\........\compare.vhd
..........\........\..........\下载文件
..........\........\..........\........\compare.bit
..........\........\..........\锁脚文件
..........\........\..........\........\compare.ucf
..........\........\数据分配器和数据选择器的设计
..........\........\............................\数据分配器
..........\........\............................\..........\VHDL程序
..........\........\............................\..........\........\data_c.vhd
..........\........\............................\..........\下载文件
..........\........\............................\..........\........\data_c.bit
..........\........\............................\..........\锁脚文件
..........\........\............................\..........\........\data_c.ucf
..........\........\............................\数据选择器
..........\........\............................\..........\VHDL程序
..........\........\............................\..........\........\c_data.vhd
..........\........\............................\..........\下载文件
..........\........\............................\..........\........\c_data.bit
..........\........\............................\..........\锁脚文件
..........\........\............................\..........\........\c_data.ucf
..........\........\普通寄存器
..........\........\..........\VHDL程序
..........\........\..........\........\reg.vhd
..........\........\..........\下载文件
..........\........\..........\........\reg.bit
..........\........\..........\锁脚文件
..........\........\..........\........\reg.ucf
..........\........\移位寄存器
..........\........\..........\VHDL程序
..........\........\..........\........\reg_shift.vhd
..........\........\..........\下载文件
..........\........\..........\........\reg_shift.bit
..........\........\..........\锁脚文件
..........\........\..........\........\reg_shift.ucf
..........\........\编码器和译码器的设计
..........\........\....................\优先编码器
..........\........\....................\..........\VHDL程序
..........\........\....................\..........\........\code_p.vhd
..........\........\....................\..........\下载文件
..........\........\....................\..........\........\code_p.bit
..........\........\....................\..........\锁脚文件
..........\........\....................\..........\........\code_p.ucf
..........\........\....................\普通编码器
..........\........\....................\..........\VHDL程序
..........\.....
交通灯的设计
............\VHDL程序
............\........\dynamic_display.vhd
............\........\state_machine.vhd
............\........\top_traffic_light1.vhd
............\........\yellowflash.vhd
............\下载文件
............\........\top_traffic_light1.bit
............\锁脚文件
............\........\top_traffic.ucf
基础性试验
..........\交通灯的设计
..........\............\VHDL程序
..........\............\........\dynamic_display.vhd
..........\............\........\state_machine.vhd
..........\............\........\top_traffic_light1.vhd
..........\............\........\yellowflash.vhd
..........\............\下载文件
..........\............\........\top_traffic_light1.bit
..........\............\锁脚文件
..........\............\........\top_traffic.ucf
..........\基础试验
..........\........\LED显示试验
..........\........\...........\VHDL文件
..........\........\...........\........\led.vhd
..........\........\...........\下载文件
..........\........\...........\........\led.bit
..........\........\...........\........\led_cclktemp.bit
..........\........\...........\锁脚文件
..........\........\...........\........\led.ucf
..........\........\按键防抖动
..........\........\..........\VHDL文件
..........\........\..........\........\button_test.vhd
..........\........\..........\下载文件
..........\........\..........\........\button_test.bit
..........\........\..........\锁脚文件
..........\........\..........\........\button_test.ucf
..........\........\数值比较器
..........\........\..........\VHDL文件
..........\........\..........\........\compare.vhd
..........\........\..........\下载文件
..........\........\..........\........\compare.bit
..........\........\..........\锁脚文件
..........\........\..........\........\compare.ucf
..........\........\数据分配器和数据选择器的设计
..........\........\............................\数据分配器
..........\........\............................\..........\VHDL程序
..........\........\............................\..........\........\data_c.vhd
..........\........\............................\..........\下载文件
..........\........\............................\..........\........\data_c.bit
..........\........\............................\..........\锁脚文件
..........\........\............................\..........\........\data_c.ucf
..........\........\............................\数据选择器
..........\........\............................\..........\VHDL程序
..........\........\............................\..........\........\c_data.vhd
..........\........\............................\..........\下载文件
..........\........\............................\..........\........\c_data.bit
..........\........\............................\..........\锁脚文件
..........\........\............................\..........\........\c_data.ucf
..........\........\普通寄存器
..........\........\..........\VHDL程序
..........\........\..........\........\reg.vhd
..........\........\..........\下载文件
..........\........\..........\........\reg.bit
..........\........\..........\锁脚文件
..........\........\..........\........\reg.ucf
..........\........\移位寄存器
..........\........\..........\VHDL程序
..........\........\..........\........\reg_shift.vhd
..........\........\..........\下载文件
..........\........\..........\........\reg_shift.bit
..........\........\..........\锁脚文件
..........\........\..........\........\reg_shift.ucf
..........\........\编码器和译码器的设计
..........\........\....................\优先编码器
..........\........\....................\..........\VHDL程序
..........\........\....................\..........\........\code_p.vhd
..........\........\....................\..........\下载文件
..........\........\....................\..........\........\code_p.bit
..........\........\....................\..........\锁脚文件
..........\........\....................\..........\........\code_p.ucf
..........\........\....................\普通编码器
..........\........\....................\..........\VHDL程序
..........\.....