文件名称:exp1
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很好的NIOS程序，包括了综合和仿真文件。-NIOS good procedures, including a comprehensive and simulation files.
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下载文件列表
exp1
....\adc_clk.v
....\adc_cs.v
....\adc_di.v
....\adc_din.v
....\adc_do.v
....\adc_dout.v
....\cmp_state.ini
....\cpu_0.ocp
....\cpu_0.v
....\cpu_0.vo
....\cpu_0_jtag_debug_module.v
....\cpu_0_jtag_debug_module_wrapper.v
....\cpu_0_ociram_default_contents.mif
....\cpu_0_test_bench.v
....\cpu_32.bsf
....\cpu_32.ptf
....\cpu_32.ptf.bak
....\cpu_32.v
....\cpu_32_generation_script
....\cpu_32_log.txt
....\cpu_32_setup_quartus.tcl
....\cpu_32_sim
....\..........\atail-f.pl
....\..........\cpu_0_ociram_default_contents.dat
....\..........\cpu_0_ociram_default_contents.hex
....\..........\create_cpu_32_project.do
....\..........\debug_input_mutex.dat
....\..........\debug_input_stream.dat
....\..........\debug_log.bat
....\..........\debug_output_stream.dat
....\..........\ic_tag_ram.dat
....\..........\ic_tag_ram.hex
....\..........\list_presets.do
....\..........\modelsim.tcl
....\..........\rf_ram_a.dat
....\..........\rf_ram_a.hex
....\..........\rf_ram_b.dat
....\..........\rf_ram_b.hex
....\..........\setup_sim.do
....\..........\sram.dat
....\..........\sram.sym
....\..........\virtuals.do
....\..........\wave_presets.do
....\db
....\..\altsyncram_5k41.tdf
....\..\altsyncram_7pv.tdf
....\..\altsyncram_8d21.tdf
....\..\altsyncram_9k41.tdf
....\..\altsyncram_bhc1.tdf
....\..\altsyncram_ept1.tdf
....\..\altsyncram_gd41.tdf
....\..\altsyncram_gpm1.tdf
....\..\altsyncram_hd41.tdf
....\..\altsyncram_pj41.tdf
....\..\a_dpfifo_83p.tdf
....\..\a_fefifo_7cf.tdf
....\..\cntr_9c7.tdf
....\..\cntr_rd8.tdf
....\..\decode_9ie.tdf
....\..\dpram_75p.tdf
....\..\example.asm.qmsg
....\..\example.cbx.xml
....\..\example.cmp.cdb
....\..\example.cmp.hdb
....\..\example.cmp.rdb
....\..\example.cmp.tdb
....\..\example.cmp0.ddb
....\..\example.db_info
....\..\example.eco.cdb
....\..\example.fit.qmsg
....\..\example.hier_info
....\..\example.hif
....\..\example.map.cdb
....\..\example.map.hdb
....\..\example.map.qmsg
....\..\example.pre_map.cdb
....\..\example.pre_map.hdb
....\..\example.psp
....\..\example.qpf
....\..\example.rtlv.hdb
....\..\example.rtlv_sg.cdb
....\..\example.rtlv_sg_swap.cdb
....\..\example.sgdiff.cdb
....\..\example.sgdiff.hdb
....\..\example.signalprobe.cdb
....\..\example.sld_design_entry.sci
....\..\example.sld_design_entry_dsc.sci
....\..\example.smp_dump.txt
....\..\example.syn_hier_info
....\..\example.tan.qmsg
....\..\example_cmp.qrpt
....\..\scfifo_1to.tdf
....\debug.v
....\example.asm.rpt
....\example.bdf
....\example.cdf
....\example.done
....\example.fit.eqn
....\example.fit.rpt
....\adc_clk.v
....\adc_cs.v
....\adc_di.v
....\adc_din.v
....\adc_do.v
....\adc_dout.v
....\cmp_state.ini
....\cpu_0.ocp
....\cpu_0.v
....\cpu_0.vo
....\cpu_0_jtag_debug_module.v
....\cpu_0_jtag_debug_module_wrapper.v
....\cpu_0_ociram_default_contents.mif
....\cpu_0_test_bench.v
....\cpu_32.bsf
....\cpu_32.ptf
....\cpu_32.ptf.bak
....\cpu_32.v
....\cpu_32_generation_script
....\cpu_32_log.txt
....\cpu_32_setup_quartus.tcl
....\cpu_32_sim
....\..........\atail-f.pl
....\..........\cpu_0_ociram_default_contents.dat
....\..........\cpu_0_ociram_default_contents.hex
....\..........\create_cpu_32_project.do
....\..........\debug_input_mutex.dat
....\..........\debug_input_stream.dat
....\..........\debug_log.bat
....\..........\debug_output_stream.dat
....\..........\ic_tag_ram.dat
....\..........\ic_tag_ram.hex
....\..........\list_presets.do
....\..........\modelsim.tcl
....\..........\rf_ram_a.dat
....\..........\rf_ram_a.hex
....\..........\rf_ram_b.dat
....\..........\rf_ram_b.hex
....\..........\setup_sim.do
....\..........\sram.dat
....\..........\sram.sym
....\..........\virtuals.do
....\..........\wave_presets.do
....\db
....\..\altsyncram_5k41.tdf
....\..\altsyncram_7pv.tdf
....\..\altsyncram_8d21.tdf
....\..\altsyncram_9k41.tdf
....\..\altsyncram_bhc1.tdf
....\..\altsyncram_ept1.tdf
....\..\altsyncram_gd41.tdf
....\..\altsyncram_gpm1.tdf
....\..\altsyncram_hd41.tdf
....\..\altsyncram_pj41.tdf
....\..\a_dpfifo_83p.tdf
....\..\a_fefifo_7cf.tdf
....\..\cntr_9c7.tdf
....\..\cntr_rd8.tdf
....\..\decode_9ie.tdf
....\..\dpram_75p.tdf
....\..\example.asm.qmsg
....\..\example.cbx.xml
....\..\example.cmp.cdb
....\..\example.cmp.hdb
....\..\example.cmp.rdb
....\..\example.cmp.tdb
....\..\example.cmp0.ddb
....\..\example.db_info
....\..\example.eco.cdb
....\..\example.fit.qmsg
....\..\example.hier_info
....\..\example.hif
....\..\example.map.cdb
....\..\example.map.hdb
....\..\example.map.qmsg
....\..\example.pre_map.cdb
....\..\example.pre_map.hdb
....\..\example.psp
....\..\example.qpf
....\..\example.rtlv.hdb
....\..\example.rtlv_sg.cdb
....\..\example.rtlv_sg_swap.cdb
....\..\example.sgdiff.cdb
....\..\example.sgdiff.hdb
....\..\example.signalprobe.cdb
....\..\example.sld_design_entry.sci
....\..\example.sld_design_entry_dsc.sci
....\..\example.smp_dump.txt
....\..\example.syn_hier_info
....\..\example.tan.qmsg
....\..\example_cmp.qrpt
....\..\scfifo_1to.tdf
....\debug.v
....\example.asm.rpt
....\example.bdf
....\example.cdf
....\example.done
....\example.fit.eqn
....\example.fit.rpt