文件名称:DDR_32Mx16_SimulationModel
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sdram的仿真模型，包括的多个不同的模型，用于仿真-SDRAM simulation model, including a number of different models for the simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DDR_32Mx16_IBIS.zip
DDR_32MX16_SPICE
................\DDR_GC_32MX16_HY5DU121622BTP_SPICE
................\..................................\512MDDR.model
................\..................................\512MDDR.skew
................\..................................\512MDDR_CA.sp
................\..................................\512MDDR_CLK.sp
................\..................................\512MDDR_DM.sp
................\..................................\512MDDR_DQ.sp
................\..................................\66tsop.lib
................\..................................\HY5DU121622BTP_Spice_Model.pdf
................\..................................\HY5DU121622BTP_Spice_Model.ppt
................\..................................\mode_control.lib
................\DDR_PC_32MX16_HY5DU121622AT_SPICE
................\.................................\512DDR_ca.sp
................\.................................\512DDR_clk.sp
................\.................................\512DDR_dm.sp
................\.................................\512DDR_dq.sp
................\.................................\66tsop.lib
................\.................................\HY5DU121622ATP_Spice_Model_Aug2004.pdf
................\.................................\HY5DU121622ATP_Spice_Model_Aug2004.ppt
................\.................................\max.inc
................\.................................\min.inc
................\.................................\mode_control.lib
................\.................................\SCH_CA.inc
................\.................................\SCH_CLK.inc
................\.................................\SCH_DM.inc
................\.................................\SCH_DQ.inc
................\.................................\typ.inc
DDR_32Mx16_Verilog
..................\DDR_1st_32Mx16_HY5DU121622T_VERILOG
..................\...................................\DDR_1st_hy5du121622t.vp.vcs
..................\...................................\DDR_1st_hy5du121622t.vp.xl
..................\DDR_PC_32Mx16_HY5DU121622AT_VERILOG
..................\...................................\DDR_PC_32Mx16_HY5DU121622AT.vcs
..................\...................................\DDR_PC_32Mx16_HY5DU121622AT.xl
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)
...........................................\DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim
...........................................\.......................................\work
...........................................\.......................................\....\hy5du121622at
...........................................\.......................................\....\.............\behavioral_model_hy5du121622at.asm
...........................................\.......................................\....\.............\behavioral_model_hy5du121622at.dat
...........................................\.......................................\....\.............\_primary.dat
...........................................\.......................................\....\hy5du121622at_pack
...........................................\.......................................\....\..................\body.asm
...........................................\.......................................\....\..................\body.dat
...........................................\.......................................\....\..................\_primary.dat
...........................................\.......................................\....\..................\_vhdl.asm
...........................................\.......................................\....\_info
...........................................\DDR_PC_32Mx16_HY5DU121622A(L)T_VSS
...........................................\..................................\README
...........................................\..................................\work
...........................................\..................................\....\HY5DU121622AT.mra
...........................................\...................
DDR_32MX16_SPICE
................\DDR_GC_32MX16_HY5DU121622BTP_SPICE
................\..................................\512MDDR.model
................\..................................\512MDDR.skew
................\..................................\512MDDR_CA.sp
................\..................................\512MDDR_CLK.sp
................\..................................\512MDDR_DM.sp
................\..................................\512MDDR_DQ.sp
................\..................................\66tsop.lib
................\..................................\HY5DU121622BTP_Spice_Model.pdf
................\..................................\HY5DU121622BTP_Spice_Model.ppt
................\..................................\mode_control.lib
................\DDR_PC_32MX16_HY5DU121622AT_SPICE
................\.................................\512DDR_ca.sp
................\.................................\512DDR_clk.sp
................\.................................\512DDR_dm.sp
................\.................................\512DDR_dq.sp
................\.................................\66tsop.lib
................\.................................\HY5DU121622ATP_Spice_Model_Aug2004.pdf
................\.................................\HY5DU121622ATP_Spice_Model_Aug2004.ppt
................\.................................\max.inc
................\.................................\min.inc
................\.................................\mode_control.lib
................\.................................\SCH_CA.inc
................\.................................\SCH_CLK.inc
................\.................................\SCH_DM.inc
................\.................................\SCH_DQ.inc
................\.................................\typ.inc
DDR_32Mx16_Verilog
..................\DDR_1st_32Mx16_HY5DU121622T_VERILOG
..................\...................................\DDR_1st_hy5du121622t.vp.vcs
..................\...................................\DDR_1st_hy5du121622t.vp.xl
..................\DDR_PC_32Mx16_HY5DU121622AT_VERILOG
..................\...................................\DDR_PC_32Mx16_HY5DU121622AT.vcs
..................\...................................\DDR_PC_32Mx16_HY5DU121622AT.xl
DDR_PC_32Mx16_HY5DU121622A(L)T_VHDL(Rev0.1)
...........................................\DDR_PC_32Mx16_HY5DU121622A(L)T_ModelSim
...........................................\.......................................\work
...........................................\.......................................\....\hy5du121622at
...........................................\.......................................\....\.............\behavioral_model_hy5du121622at.asm
...........................................\.......................................\....\.............\behavioral_model_hy5du121622at.dat
...........................................\.......................................\....\.............\_primary.dat
...........................................\.......................................\....\hy5du121622at_pack
...........................................\.......................................\....\..................\body.asm
...........................................\.......................................\....\..................\body.dat
...........................................\.......................................\....\..................\_primary.dat
...........................................\.......................................\....\..................\_vhdl.asm
...........................................\.......................................\....\_info
...........................................\DDR_PC_32Mx16_HY5DU121622A(L)T_VSS
...........................................\..................................\README
...........................................\..................................\work
...........................................\..................................\....\HY5DU121622AT.mra
...........................................\...................