文件名称:Source
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I2C总线的verilog实现，包括主模块和几个子模块，已仿真实现-Verilog I2C Bus realize, including the main module and several sub-modules have been simulation
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下载文件列表
Source
......\i2c.v
......\i2c_clk.v
......\i2c_rreg.v
......\i2c_st.v
......\i2c_tbuf.v
......\i2c_wreg.v
......\transcript
......\i2c.v
......\i2c_clk.v
......\i2c_rreg.v
......\i2c_st.v
......\i2c_tbuf.v
......\i2c_wreg.v
......\transcript