文件名称:DecimationFilterDesignforDDCandImplementingItwithF
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本文介绍了在数字下变频(DDC) 中的抽取滤波器系统设计方法和具体实现方案。采用CIC 滤波器、HB
滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性-This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design
滤波器、FIR 滤波器三级级联的方式来降低采样率。通过实际验证,证明了设计的可行性-This article describes the digital down conversion (DDC) of the decimation filter system design methods and concrete realization of the program. Using CIC filter, HB filter, FIR filter cascade three-level approach to reduce the sampling rate. Through the actual authentication, to prove the feasibility of the design
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DDC中的抽取滤波器设计及FPGA实现.pdf