文件名称:jianpansaomiao__verilog

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 717kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • zhang******
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

一个veriloghdl编写的键盘扫描程序-Veriloghdl the preparation of a keyboard scanner
(系统自动生成,下载前可以参看下载内容)

下载文件列表

ProjNav

.......\automake.log

.......\behavioral_sim.do

.......\glbl.v

.......\KeypadScan.bak

.......\KeypadScan.bld

.......\KeypadScan.cel

.......\KeypadScan.cmd_log

.......\KeypadScan.cxt

.......\KeypadScan.gyd

.......\KeypadScan.lfp

.......\KeypadScan.log

.......\KeypadScan.lso

.......\KeypadScan.mfd

.......\KeypadScan.nga

.......\KeypadScan.ngc

.......\KeypadScan.ngd

.......\KeypadScan.ngr

.......\KeypadScan.par_nlf

.......\KeypadScan.pnx

.......\KeypadScan.prj

.......\KeypadScan.rpt

.......\KeypadScan.stx

.......\KeypadScan.syr

.......\KeypadScan.tspec

.......\KeypadScan.ucf

.......\KeypadScan.ucf.untf

.......\KeypadScan.v

.......\KeypadScan.vcd

.......\KeypadScan.versim_par

.......\KeypadScan.vm6

.......\KeypadScan.xml

.......\KeypadScan._hrpt

.......\KeypadScan_build.xml

.......\KeypadScan_pad.csv

.......\KeypadScan_tb_v_tf.fdo

.......\KeypadScan_tb_v_tf.tdo

.......\KeypadScan_tb_v_tf.udo

.......\KeypadScan_timesim.nlf

.......\KeypadScan_timesim.sdf

.......\KeypadScan_timesim.v

.......\KeypadScan_vhdl.prj

.......\post_fit_sim.do

.......\ProjNav.dhp

.......\ProjNav.npl

.......\t1.dat

.......\t1.phd

.......\t55.dat

.......\t55.phd

.......\t6.dat

.......\t6.phd

.......\tb.asv

.......\tb.bak

.......\tb.v

.......\tmperr.err

.......\transcript

.......\userlang.tpl

.......\vsim.wlf

.......\wave.do

.......\wave_timing.do

.......\work

.......\....\@keypad@scan

.......\....\............\verilog.asm

.......\....\............\_primary.dat

.......\....\............\_primary.vhd

.......\....\@keypad@scan_tb_v_tf

.......\....\....................\verilog.asm

.......\....\....................\_primary.dat

.......\....\....................\_primary.vhd

.......\....\glbl

.......\....\....\verilog.asm

.......\....\....\_primary.dat

.......\....\....\_primary.vhd

.......\....\_info

.......\xst

.......\...\work

.......\...\....\hdllib.ref

.......\...\....\vlg4F

.......\...\....\.....\KeypadScan.bin

.......\_ngo

.......\....\netlist.lst

.......\_pace.ucf

.......\__projnav

.......\.........\KeypadScan.xst

.......\.........\KeypadScan_edfTOngd_tcl.rsp

.......\.........\parentAssignPackagePinsApp_tcl.rsp

.......\.........\parentCreateTimingConstraintsApp_tcl.rsp

.......\.........\parentEditConstraintsTextApp_tcl.rsp

.......\.........\ProjNav.gfl

.......\.........\ProjNav_flowplus.gfl

.......\.........\runXst_tcl.rsp

.......\__projnav.log

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