文件名称:clock
介绍说明--下载内容均来自于网络,请自行研究使用
这是一个实现时分秒的时钟功能的源码,采用vhdl语言编写,已写好led驱动,可直接在数码管上显示-Realize this is an accurate clock function when the source code, the use of VHDL language has been written led drive directly in the digital tube display
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clock
.....\clock.asm.rpt
.....\clock.bsf
.....\clock.done
.....\clock.dpf
.....\clock.fit.eqn
.....\clock.fit.rpt
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.eqn
.....\clock.map.rpt
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.qws
.....\clock.sim.rpt
.....\clock.sof
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.vhd
.....\clock.vwf
.....\counter10.bsf
.....\counter10.vhd
.....\counter24.bsf
.....\counter24.vhd
.....\counter6.bsf
.....\counter6.vhd
.....\db
.....\..\clock.analyze_file.qmsg
.....\..\clock.asm.qmsg
.....\..\clock.cbx.xml
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.qrpt
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.dbp
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.eds_overflow
.....\..\clock.fit.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.qmsg
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.psp
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.signalprobe.cdb
.....\..\clock.sim.hdb
.....\..\clock.sim.qmsg
.....\..\clock.sim.qrpt
.....\..\clock.sim.rdb
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\decoder.bsf
.....\decoder.vhd
.....\sopc_builder_debug_log.txt
.....\Waveform1.vwf
.....\Waveform2.vwf
.....\Waveform3.vwf
.....\clock.asm.rpt
.....\clock.bsf
.....\clock.done
.....\clock.dpf
.....\clock.fit.eqn
.....\clock.fit.rpt
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.eqn
.....\clock.map.rpt
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.qws
.....\clock.sim.rpt
.....\clock.sof
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.vhd
.....\clock.vwf
.....\counter10.bsf
.....\counter10.vhd
.....\counter24.bsf
.....\counter24.vhd
.....\counter6.bsf
.....\counter6.vhd
.....\db
.....\..\clock.analyze_file.qmsg
.....\..\clock.asm.qmsg
.....\..\clock.cbx.xml
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.qrpt
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.dbp
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.eds_overflow
.....\..\clock.fit.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.qmsg
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.psp
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.signalprobe.cdb
.....\..\clock.sim.hdb
.....\..\clock.sim.qmsg
.....\..\clock.sim.qrpt
.....\..\clock.sim.rdb
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\decoder.bsf
.....\decoder.vhd
.....\sopc_builder_debug_log.txt
.....\Waveform1.vwf
.....\Waveform2.vwf
.....\Waveform3.vwf