文件名称:MyFPGA
介绍说明－－下载内容均来自于网络，请自行研究使用
FPGA系统的sram的软仿真设计，可以实现按位写，按位读。-SRAM FPGA system soft simulation designed to realize bitwise write bitwise Reading.
相关搜索： fpga
(系统自动生成,下载前可以参看下载内容)
下载文件列表
MyFPGA
......\.untf
......\automake.log
......\coregen.log
......\coregen.prj
......\force.txt
......\MyFPGA.dhp
......\MyFPGA.npl
......\mysimwork
......\.........\my_sram
......\.........\.......\behavioral.asm
......\.........\.......\behavioral.dat
......\.........\.......\_primary.dat
......\.........\my_sram_timesim.sdf
......\.........\my_sram_timesim.vhd
......\.........\_info
......\my_sram.bld
......\my_sram.cmd_log
......\my_sram.lso
......\my_sram.mrp
......\my_sram.nc1
......\my_sram.ncd
......\my_sram.ngc
......\my_sram.ngd
......\my_sram.ngm
......\my_sram.ngr
......\my_sram.pad
......\my_sram.pad_txt
......\my_sram.par
......\my_sram.par_nlf
......\my_sram.pcf
......\my_sram.placed_ncd_tracker
......\my_sram.prj
......\my_sram.routed_ncd_tracker
......\my_sram.spl
......\my_sram.stx
......\my_sram.sym
......\my_sram.syr
......\my_sram.twr
......\my_sram.twx
......\my_sram.ucf
......\my_sram.ucf.untf
......\my_sram.vhd
......\my_sram.vhdsim_par
......\my_sram.vhdsim_xlate
......\my_sram.vhi
......\my_sram.xlate_nlf
......\my_sram.xpi
......\my_sram_last_par.ncd
......\my_sram_map.ncd
......\my_sram_map.ngm
......\my_sram_pad.csv
......\my_sram_pad.txt
......\my_sram_test_vhd_tb.fdo
......\my_sram_test_vhd_tb.tdo
......\my_sram_test_vhd_tb.udo
......\my_sram_timesim.nlf
......\my_sram_timesim.sdf
......\my_sram_timesim.vhd
......\my_sram_translate.nlf
......\my_sram_translate.vhd
......\pepExtractor.prj
......\prjname.lso
......\results.txt
......\sram.cmd_log
......\sram.lso
......\sram.ngr
......\sram.prj
......\sram.stx
......\sram.syr
......\sram_vhdl.prj
......\transcript
......\userlang.tpl
......\vsim.wlf
......\work
......\....\my_sram
......\....\.......\behavioral.asm
......\....\.......\behavioral.dat
......\....\.......\_primary.dat
......\....\_info
......\xst
......\...\work
......\...\....\hdllib.ref
......\...\....\hdpdeps.ref
......\...\....\sub00
......\...\....\.....\vhpl00.vho
......\...\....\.....\vhpl01.vho
......\...\....\.....\vhpl02.vho
......\...\....\.....\vhpl03.vho
......\_ngo
......\....\netlist.lst
......\__projnav
......\.........\coregen.rsp
......\.........\createTB.err
......\.........\ednTOngd_tcl.rsp
......\.........\hb_cmds
......\.........\map.log
......\.........\MyFPGA.gfl
......\.........\MyFPGA_flowplus.gfl
......\.........\MyFPJA.gfl
......\.untf
......\automake.log
......\coregen.log
......\coregen.prj
......\force.txt
......\MyFPGA.dhp
......\MyFPGA.npl
......\mysimwork
......\.........\my_sram
......\.........\.......\behavioral.asm
......\.........\.......\behavioral.dat
......\.........\.......\_primary.dat
......\.........\my_sram_timesim.sdf
......\.........\my_sram_timesim.vhd
......\.........\_info
......\my_sram.bld
......\my_sram.cmd_log
......\my_sram.lso
......\my_sram.mrp
......\my_sram.nc1
......\my_sram.ncd
......\my_sram.ngc
......\my_sram.ngd
......\my_sram.ngm
......\my_sram.ngr
......\my_sram.pad
......\my_sram.pad_txt
......\my_sram.par
......\my_sram.par_nlf
......\my_sram.pcf
......\my_sram.placed_ncd_tracker
......\my_sram.prj
......\my_sram.routed_ncd_tracker
......\my_sram.spl
......\my_sram.stx
......\my_sram.sym
......\my_sram.syr
......\my_sram.twr
......\my_sram.twx
......\my_sram.ucf
......\my_sram.ucf.untf
......\my_sram.vhd
......\my_sram.vhdsim_par
......\my_sram.vhdsim_xlate
......\my_sram.vhi
......\my_sram.xlate_nlf
......\my_sram.xpi
......\my_sram_last_par.ncd
......\my_sram_map.ncd
......\my_sram_map.ngm
......\my_sram_pad.csv
......\my_sram_pad.txt
......\my_sram_test_vhd_tb.fdo
......\my_sram_test_vhd_tb.tdo
......\my_sram_test_vhd_tb.udo
......\my_sram_timesim.nlf
......\my_sram_timesim.sdf
......\my_sram_timesim.vhd
......\my_sram_translate.nlf
......\my_sram_translate.vhd
......\pepExtractor.prj
......\prjname.lso
......\results.txt
......\sram.cmd_log
......\sram.lso
......\sram.ngr
......\sram.prj
......\sram.stx
......\sram.syr
......\sram_vhdl.prj
......\transcript
......\userlang.tpl
......\vsim.wlf
......\work
......\....\my_sram
......\....\.......\behavioral.asm
......\....\.......\behavioral.dat
......\....\.......\_primary.dat
......\....\_info
......\xst
......\...\work
......\...\....\hdllib.ref
......\...\....\hdpdeps.ref
......\...\....\sub00
......\...\....\.....\vhpl00.vho
......\...\....\.....\vhpl01.vho
......\...\....\.....\vhpl02.vho
......\...\....\.....\vhpl03.vho
......\_ngo
......\....\netlist.lst
......\__projnav
......\.........\coregen.rsp
......\.........\createTB.err
......\.........\ednTOngd_tcl.rsp
......\.........\hb_cmds
......\.........\map.log
......\.........\MyFPGA.gfl
......\.........\MyFPGA_flowplus.gfl
......\.........\MyFPJA.gfl