文件名称:colour_light
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一个圣诞彩灯控制芯片的vrilog源代码，可以综合，经过FPGA验证，产生四路输出，控制四路彩灯，有跑马闪，星闪等多种功能-A Christmas lantern control chips vrilog source code, can be integrated, after FPGA validation, resulting in four outputs, four control lantern, a Happy flash, sing a variety of functions such as flash
相关搜索： vrilog
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下载文件列表
final_simple8
.............\bright_clk.v
.............\chip_editor.acv
.............\clk_select.v
.............\cmp_state.ini
.............\colorlight.qpf
.............\colorlight.qws
.............\d.v
.............\dark_clk.v
.............\db
.............\..\add_sub_6ph.tdf
.............\..\add_sub_7ph.tdf
.............\..\add_sub_onh.tdf
.............\..\colorlight.db_info
.............\..\colorlight.project.hdb
.............\..\colorlight.top.sld_design_entry.sci
.............\..\top.asm.qmsg
.............\..\top.cbx.xml
.............\..\top.cmp.cdb
.............\..\top.cmp.hdb
.............\..\top.cmp.rdb
.............\..\top.cmp.tdb
.............\..\top.cmp0.ddb
.............\..\top.db_info
.............\..\top.eco.cdb
.............\..\top.fit.qmsg
.............\..\top.hier_info
.............\..\top.hif
.............\..\top.map.cdb
.............\..\top.map.hdb
.............\..\top.map.qmsg
.............\..\top.pre_map.cdb
.............\..\top.pre_map.hdb
.............\..\top.psp
.............\..\top.rtlv.hdb
.............\..\top.rtlv_sg.cdb
.............\..\top.rtlv_sg_swap.cdb
.............\..\top.sgdiff.cdb
.............\..\top.sgdiff.hdb
.............\..\top.signalprobe.cdb
.............\..\top.sld_design_entry.sci
.............\..\top.sld_design_entry_dsc.sci
.............\..\top.syn_hier_info
.............\..\top.tan.qmsg
.............\..\top_cmp.qrpt
.............\..\top_hier_info
.............\..\top_sim.qrpt
.............\..\top_syn_hier_info
.............\delay.v
.............\div_132.v
.............\div_16500.v
.............\div_165000.v
.............\div_25.v
.............\div_4.v
.............\div_5000.v
.............\huayang.v
.............\huayangclk.v
.............\medium1_clk.v
.............\medium2_clk.v
.............\medium3_clk.v
.............\medium4_clk.v
.............\medium5_clk.v
.............\medium_clk.v
.............\model1.v
.............\model1_top.v
.............\model2.v
.............\model2_fast.v
.............\model2_huayang.v
.............\model2_select.v
.............\model2_slow.v
.............\model2_top.v
.............\model3.v
.............\model3_fast.v
.............\model3_huayang.v
.............\model3_select.v
.............\model3_slow.v
.............\model3_top.v
.............\model3_veryslow.v
.............\model4.v
.............\model4_fast.v
.............\model4_huayang.v
.............\model4_select.v
.............\model4_slow.v
.............\model4_top.v
.............\model5.v
.............\model5_3slow_inv.v
.............\model5_huayang.v
.............\model5_select.v
.............\model5_top.v
.............\model6.v
.............\model6_fast.v
.............\model6_huayang.v
.............\model6_select.v
.............\model6_slow.v
.............\model6_top.v
.............\model7.v
.............\model7_huayang.v
.............\model7_select.v
.............\model7_top.v
.............\model8.v
.............\bright_clk.v
.............\chip_editor.acv
.............\clk_select.v
.............\cmp_state.ini
.............\colorlight.qpf
.............\colorlight.qws
.............\d.v
.............\dark_clk.v
.............\db
.............\..\add_sub_6ph.tdf
.............\..\add_sub_7ph.tdf
.............\..\add_sub_onh.tdf
.............\..\colorlight.db_info
.............\..\colorlight.project.hdb
.............\..\colorlight.top.sld_design_entry.sci
.............\..\top.asm.qmsg
.............\..\top.cbx.xml
.............\..\top.cmp.cdb
.............\..\top.cmp.hdb
.............\..\top.cmp.rdb
.............\..\top.cmp.tdb
.............\..\top.cmp0.ddb
.............\..\top.db_info
.............\..\top.eco.cdb
.............\..\top.fit.qmsg
.............\..\top.hier_info
.............\..\top.hif
.............\..\top.map.cdb
.............\..\top.map.hdb
.............\..\top.map.qmsg
.............\..\top.pre_map.cdb
.............\..\top.pre_map.hdb
.............\..\top.psp
.............\..\top.rtlv.hdb
.............\..\top.rtlv_sg.cdb
.............\..\top.rtlv_sg_swap.cdb
.............\..\top.sgdiff.cdb
.............\..\top.sgdiff.hdb
.............\..\top.signalprobe.cdb
.............\..\top.sld_design_entry.sci
.............\..\top.sld_design_entry_dsc.sci
.............\..\top.syn_hier_info
.............\..\top.tan.qmsg
.............\..\top_cmp.qrpt
.............\..\top_hier_info
.............\..\top_sim.qrpt
.............\..\top_syn_hier_info
.............\delay.v
.............\div_132.v
.............\div_16500.v
.............\div_165000.v
.............\div_25.v
.............\div_4.v
.............\div_5000.v
.............\huayang.v
.............\huayangclk.v
.............\medium1_clk.v
.............\medium2_clk.v
.............\medium3_clk.v
.............\medium4_clk.v
.............\medium5_clk.v
.............\medium_clk.v
.............\model1.v
.............\model1_top.v
.............\model2.v
.............\model2_fast.v
.............\model2_huayang.v
.............\model2_select.v
.............\model2_slow.v
.............\model2_top.v
.............\model3.v
.............\model3_fast.v
.............\model3_huayang.v
.............\model3_select.v
.............\model3_slow.v
.............\model3_top.v
.............\model3_veryslow.v
.............\model4.v
.............\model4_fast.v
.............\model4_huayang.v
.............\model4_select.v
.............\model4_slow.v
.............\model4_top.v
.............\model5.v
.............\model5_3slow_inv.v
.............\model5_huayang.v
.............\model5_select.v
.............\model5_top.v
.............\model6.v
.............\model6_fast.v
.............\model6_huayang.v
.............\model6_select.v
.............\model6_slow.v
.............\model6_top.v
.............\model7.v
.............\model7_huayang.v
.............\model7_select.v
.............\model7_top.v
.............\model8.v