文件名称:suanshuluojidanyuan
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1. 课程设计的任务
本次课程设计的任务是实现一个算术逻辑运算单元，使之能够完成不带进位位算术、逻辑八位二进制数的运算。由具有扩展能力强，结构简单清晰，连线方便快捷的总线结构作为系统结构。系统测试采用在系统的每个总线上设置测试孔。采用闪存存储数据，系统可以通过监测模块来修改和控制微程序的运行。
采用若干种类的芯片组作为运算器和数据输入输出缓冲、输入锁存器，其中2片74LS181构成8位字长的ALU单元是算术逻辑运算单元核心。
-1. The task of curriculum design curriculum design of this task is the realization of an arithmetic logic operation unit, so that it can not be brought into complete bit-bit arithmetic, logic 8 binary arithmetic. Expansion of capacity by a strong, clear and simple structure, convenient bus connection structure as the system architecture. System test bus in the system set up for each test hole. Store data using flash memory, the system can monitor the module to modify and control the operation of micro-procedures. The use of certain types of chipsets as a computing device and data input and output buffering, input latch, which constitute two 74LS181 word length of 8 is the arithmetic logic unit ALU FPU core.
本次课程设计的任务是实现一个算术逻辑运算单元，使之能够完成不带进位位算术、逻辑八位二进制数的运算。由具有扩展能力强，结构简单清晰，连线方便快捷的总线结构作为系统结构。系统测试采用在系统的每个总线上设置测试孔。采用闪存存储数据，系统可以通过监测模块来修改和控制微程序的运行。
采用若干种类的芯片组作为运算器和数据输入输出缓冲、输入锁存器，其中2片74LS181构成8位字长的ALU单元是算术逻辑运算单元核心。
-1. The task of curriculum design curriculum design of this task is the realization of an arithmetic logic operation unit, so that it can not be brought into complete bit-bit arithmetic, logic 8 binary arithmetic. Expansion of capacity by a strong, clear and simple structure, convenient bus connection structure as the system architecture. System test bus in the system set up for each test hole. Store data using flash memory, the system can monitor the module to modify and control the operation of micro-procedures. The use of certain types of chipsets as a computing device and data input and output buffering, input latch, which constitute two 74LS181 word length of 8 is the arithmetic logic unit ALU FPU core.
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