文件名称:code
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verilog语言写的简单八位处理器。有8个模块，可进行加法运算。-Verilog language to write a simple eight processors. There are eight modules, addition operations can be carried out.
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下载文件列表
code
....\accum.v
....\addr_decode.v
....\adr.v
....\alu.v
....\clk_gen.v
....\counter.v
....\cpu.v
....\cputop.v
....\cputop2.v
....\datactl.v
....\machine.v
....\machinectl.v
....\ram.v
....\register.v
....\rom.v
....\test2.dat
....\test2.pro
....\accum.v
....\addr_decode.v
....\adr.v
....\alu.v
....\clk_gen.v
....\counter.v
....\cpu.v
....\cputop.v
....\cputop2.v
....\datactl.v
....\machine.v
....\machinectl.v
....\ram.v
....\register.v
....\rom.v
....\test2.dat
....\test2.pro