文件名称:verilog
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verilog原理与应用
作者：Michael D. Ciletti
-Principle and Application of Verilog Author: Michael D. Ciletti
作者：Michael D. Ciletti
-Principle and Application of Verilog Author: Michael D. Ciletti
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Models and Testbenches 11_10_2004
.................................\Chapter 10
.................................\..........\ADDVB_Models_10.doc
.................................\..........\Dividers
.................................\..........\........\Divider_RR_STG.v
.................................\..........\........\Divider_STG_0.v
.................................\..........\........\Divider_STG_0_sub.v
.................................\..........\........\Divider_STG_1.v
.................................\..........\........\t_Divider_RR_STG.v
.................................\..........\........\_vti_cnf
.................................\..........\........\........\Divider_RR_STG.v
.................................\..........\........\........\Divider_STG_0.v
.................................\..........\........\........\Divider_STG_0_sub.v
.................................\..........\........\........\Divider_STG_1.v
.................................\..........\........\........\t_Divider_RR_STG.v
.................................\..........\Multipliers
.................................\..........\...........\Multiplier_ASM_0.v
.................................\..........\...........\Multiplier_ASM_1.v
.................................\..........\...........\Multiplier_Booth_STG_0.v
.................................\..........\...........\Multiplier_Implicit_1.v
.................................\..........\...........\Multiplier_Implicit_2.v
.................................\..........\...........\Multiplier_RR_ASM.v
.................................\..........\...........\Multiplier_STG_0.v
.................................\..........\...........\Multiplier_STG_1.v
.................................\..........\...........\Radix_4__STG_0.v
.................................\..........\...........\_vti_cnf
.................................\..........\...........\........\Multiplier_ASM_0.v
.................................\..........\...........\........\Multiplier_ASM_1.v
.................................\..........\...........\........\Multiplier_Booth_STG_0.v
.................................\..........\...........\........\Multiplier_Implicit_1.v
.................................\..........\...........\........\Multiplier_Implicit_2.v
.................................\..........\...........\........\Multiplier_RR_ASM.v
.................................\..........\...........\........\Multiplier_STG_0.v
.................................\..........\...........\........\Multiplier_STG_1.v
.................................\..........\...........\........\Radix_4__STG_0.v
.................................\..........\_vti_cnf
.................................\..........\........\ADDVB_Models_10.doc
.................................\Chapter 11
.................................\..........\ADDVB_Models_11.doc
.................................\..........\BIST
.................................\..........\....\ASIC_with_BIST.v
.................................\..........\....\t_ASIC_with_BIST.v
.................................\..........\....\_vti_cnf
.................................\..........\....\........\ASIC_with_BIST.v
.................................\..........\....\........\t_ASIC_with_BIST.v
.................................\..........\JTAG
.................................\..........\....\ASIC_with_TAP.v
.................................\..........\....\Boundary_Scan_Register.v
.................................\..........\....\BR_Cell.v
.................................\..........\....\BSC_Cell.v
.................................\..........\....\Instruction_Decoder.v
.................................\..........\....\Instruction_Register.v
.................................\..........\....\IR_Cell.v
.................................\..........\....\tap_controller.v
.................................\..........\....\TAP_FSM.v
.................................\..........\....\TDI_Generator.v
.................................\..........\....\TDO_Monitor.v
.................................\..........\....\t_ASIC_with
.................................\Chapter 10
.................................\..........\ADDVB_Models_10.doc
.................................\..........\Dividers
.................................\..........\........\Divider_RR_STG.v
.................................\..........\........\Divider_STG_0.v
.................................\..........\........\Divider_STG_0_sub.v
.................................\..........\........\Divider_STG_1.v
.................................\..........\........\t_Divider_RR_STG.v
.................................\..........\........\_vti_cnf
.................................\..........\........\........\Divider_RR_STG.v
.................................\..........\........\........\Divider_STG_0.v
.................................\..........\........\........\Divider_STG_0_sub.v
.................................\..........\........\........\Divider_STG_1.v
.................................\..........\........\........\t_Divider_RR_STG.v
.................................\..........\Multipliers
.................................\..........\...........\Multiplier_ASM_0.v
.................................\..........\...........\Multiplier_ASM_1.v
.................................\..........\...........\Multiplier_Booth_STG_0.v
.................................\..........\...........\Multiplier_Implicit_1.v
.................................\..........\...........\Multiplier_Implicit_2.v
.................................\..........\...........\Multiplier_RR_ASM.v
.................................\..........\...........\Multiplier_STG_0.v
.................................\..........\...........\Multiplier_STG_1.v
.................................\..........\...........\Radix_4__STG_0.v
.................................\..........\...........\_vti_cnf
.................................\..........\...........\........\Multiplier_ASM_0.v
.................................\..........\...........\........\Multiplier_ASM_1.v
.................................\..........\...........\........\Multiplier_Booth_STG_0.v
.................................\..........\...........\........\Multiplier_Implicit_1.v
.................................\..........\...........\........\Multiplier_Implicit_2.v
.................................\..........\...........\........\Multiplier_RR_ASM.v
.................................\..........\...........\........\Multiplier_STG_0.v
.................................\..........\...........\........\Multiplier_STG_1.v
.................................\..........\...........\........\Radix_4__STG_0.v
.................................\..........\_vti_cnf
.................................\..........\........\ADDVB_Models_10.doc
.................................\Chapter 11
.................................\..........\ADDVB_Models_11.doc
.................................\..........\BIST
.................................\..........\....\ASIC_with_BIST.v
.................................\..........\....\t_ASIC_with_BIST.v
.................................\..........\....\_vti_cnf
.................................\..........\....\........\ASIC_with_BIST.v
.................................\..........\....\........\t_ASIC_with_BIST.v
.................................\..........\JTAG
.................................\..........\....\ASIC_with_TAP.v
.................................\..........\....\Boundary_Scan_Register.v
.................................\..........\....\BR_Cell.v
.................................\..........\....\BSC_Cell.v
.................................\..........\....\Instruction_Decoder.v
.................................\..........\....\Instruction_Register.v
.................................\..........\....\IR_Cell.v
.................................\..........\....\tap_controller.v
.................................\..........\....\TAP_FSM.v
.................................\..........\....\TDI_Generator.v
.................................\..........\....\TDO_Monitor.v
.................................\..........\....\t_ASIC_with