文件名称:alaw_mulaw
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这是一个量化编码当中关于A律和u律压缩和扩展的源程序，程序由VerilogHDL语言编写，算法在Modelsim上进行仿真过-This is a quantization coding of them on the A law and u law compression and expansion of the source code, the program by VerilogHDL languages, algorithms in the ModelSim simulation have been carried out
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下载文件列表
alaw_mulaw
..........\a-law_compression.cr.mti
..........\a-law_compression.mpf
..........\int2alaw.v
..........\linear2ulaw.v
..........\sim_linear2ulaw.v
..........\test_int2alaw(05-29).txt
..........\test_int2alaw.v
..........\test_ulaw2int(5-29).txt
..........\test_ulaw2int.v
..........\transcript
..........\u-law_expansion.cr.mti
..........\u-law_expansion.mpf
..........\ulaw2int.v
..........\work
..........\....\int2alaw
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\test_int2alaw
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\test_ulaw2int
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\ulaw2int
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\_info
..........\a-law_compression.cr.mti
..........\a-law_compression.mpf
..........\int2alaw.v
..........\linear2ulaw.v
..........\sim_linear2ulaw.v
..........\test_int2alaw(05-29).txt
..........\test_int2alaw.v
..........\test_ulaw2int(5-29).txt
..........\test_ulaw2int.v
..........\transcript
..........\u-law_expansion.cr.mti
..........\u-law_expansion.mpf
..........\ulaw2int.v
..........\work
..........\....\int2alaw
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\test_int2alaw
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\test_ulaw2int
..........\....\.............\verilog.asm
..........\....\.............\_primary.dat
..........\....\.............\_primary.vhd
..........\....\ulaw2int
..........\....\........\verilog.asm
..........\....\........\_primary.dat
..........\....\........\_primary.vhd
..........\....\_info