文件名称:ttyscz
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运用vhdl语言编程,是数字逻辑中的电子钟!各模块及源代码都有,适合电信同学使用!-The use of VHDL language programming, digital logic electronic bell! Various modules and source code are suitable for the use of telecommunications classmates!
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下载文件列表
ttyscz
......\bbb.bsf
......\bbb.done
......\bbb.flow.rpt
......\bbb.map.rpt
......\bbb.map.summary
......\bbb.qpf
......\bbb.qsf
......\bbb.qws
......\bbb.vhd
......\bbb.vhd.bak
......\ccc.bsf
......\ccc.done
......\ccc.flow.rpt
......\ccc.map.rpt
......\ccc.map.summary
......\ccc.qpf
......\ccc.qsf
......\ccc.qws
......\ccc.vhd
......\ccc.vhd.bak
......\clock.asm.rpt
......\clock.bdf
......\clock.cdf
......\clock.done
......\clock.fit.eqn
......\clock.fit.rpt
......\clock.fit.summary
......\clock.flow.rpt
......\clock.map.eqn
......\clock.map.rpt
......\clock.map.summary
......\clock.pin
......\clock.pof
......\clock.qpf
......\clock.qsf
......\clock.qws
......\clock.sof
......\clock.tan.rpt
......\clock.tan.summary
......\clock_assignment_defaults.qdf
......\cmp_state.ini
......\disp.bsf
......\disp.done
......\disp.flow.rpt
......\disp.map.rpt
......\disp.map.summary
......\disp.qpf
......\disp.qsf
......\disp.qws
......\disp.vhd
......\disp.vhd.bak
......\fen10.bsf
......\fen10.done
......\fen10.flow.rpt
......\fen10.inc
......\fen10.map.rpt
......\fen10.map.summary
......\fen10.qpf
......\fen10.qsf
......\fen10.qws
......\fen10.vhd
......\hour.bsf
......\hour.done
......\hour.flow.rpt
......\hour.map.rpt
......\hour.map.summary
......\hour.qpf
......\hour.qsf
......\hour.qws
......\hour.vhd
......\hour.vhd.bak
......\lpm_constant0.bsf
......\lpm_constant0.inc
......\lpm_constant0.tdf
......\mian.bsf
......\mian.vhd
......\mian.vhd.bak
......\mina.bsf
......\mina.done
......\mina.flow.rpt
......\mina.map.rpt
......\mina.map.summary
......\mina.qpf
......\mina.qsf
......\mina.qws
......\mina.vhd
......\mina.vhd.bak
......\sel.bsf
......\sel.done
......\sel.flow.rpt
......\sel.map.rpt
......\sel.map.summary
......\sel.qpf
......\sel.qsf
......\sel.qws
......\sel.vhd
......\sel.vhd.bak
......\sst.bsf
......\sst.done
......\bbb.bsf
......\bbb.done
......\bbb.flow.rpt
......\bbb.map.rpt
......\bbb.map.summary
......\bbb.qpf
......\bbb.qsf
......\bbb.qws
......\bbb.vhd
......\bbb.vhd.bak
......\ccc.bsf
......\ccc.done
......\ccc.flow.rpt
......\ccc.map.rpt
......\ccc.map.summary
......\ccc.qpf
......\ccc.qsf
......\ccc.qws
......\ccc.vhd
......\ccc.vhd.bak
......\clock.asm.rpt
......\clock.bdf
......\clock.cdf
......\clock.done
......\clock.fit.eqn
......\clock.fit.rpt
......\clock.fit.summary
......\clock.flow.rpt
......\clock.map.eqn
......\clock.map.rpt
......\clock.map.summary
......\clock.pin
......\clock.pof
......\clock.qpf
......\clock.qsf
......\clock.qws
......\clock.sof
......\clock.tan.rpt
......\clock.tan.summary
......\clock_assignment_defaults.qdf
......\cmp_state.ini
......\disp.bsf
......\disp.done
......\disp.flow.rpt
......\disp.map.rpt
......\disp.map.summary
......\disp.qpf
......\disp.qsf
......\disp.qws
......\disp.vhd
......\disp.vhd.bak
......\fen10.bsf
......\fen10.done
......\fen10.flow.rpt
......\fen10.inc
......\fen10.map.rpt
......\fen10.map.summary
......\fen10.qpf
......\fen10.qsf
......\fen10.qws
......\fen10.vhd
......\hour.bsf
......\hour.done
......\hour.flow.rpt
......\hour.map.rpt
......\hour.map.summary
......\hour.qpf
......\hour.qsf
......\hour.qws
......\hour.vhd
......\hour.vhd.bak
......\lpm_constant0.bsf
......\lpm_constant0.inc
......\lpm_constant0.tdf
......\mian.bsf
......\mian.vhd
......\mian.vhd.bak
......\mina.bsf
......\mina.done
......\mina.flow.rpt
......\mina.map.rpt
......\mina.map.summary
......\mina.qpf
......\mina.qsf
......\mina.qws
......\mina.vhd
......\mina.vhd.bak
......\sel.bsf
......\sel.done
......\sel.flow.rpt
......\sel.map.rpt
......\sel.map.summary
......\sel.qpf
......\sel.qsf
......\sel.qws
......\sel.vhd
......\sel.vhd.bak
......\sst.bsf
......\sst.done