文件名称:VerilogHDL_advanced_digital_design_code_Ch7
- 所属分类：
- VHDL编程
- 资源属性：
- [WORD]
- 上传时间：
- 2012-11-26
- 文件大小：
- 46kb
- 下载次数：
- 0次
- 提 供 者：
- lianl******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
VerilogHDL_advanced_digital_design_code_Ch7
Verilog HDL 高级数字设计 源码ch7-Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch7Verilog HDL source CH7
Verilog HDL 高级数字设计 源码ch7-Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch7Verilog HDL source CH7
相关搜索： verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VerilogHDL_advanced_digital_design_code_Ch7
...........................................\ADDVB_Models_7.doc
...........................................\ADDVB_Models_7.v.txt
...........................................\Bin_Cnt_Part_RTL.v
...........................................\Bin_Cnt_Part_RTL_by_3.v
...........................................\Clock_Unit.v
...........................................\Gap_Finder.doc
...........................................\Gap_Finder.v
...........................................\RISC_SPM.v
...........................................\test_RISC_SPM.v
...........................................\t_Bin_Cnt_Part_RTL_by_3.v
...........................................\uart8_rcvr.v
...........................................\uart8_rcvr_partition.v
...........................................\UART_xmtr_Arch.v
...........................................\_vti_cnf
...........................................\........\ADDVB_Models_7.doc
...........................................\........\Bin_Cnt_Part_RTL.v
...........................................\........\Bin_Cnt_Part_RTL_by_3.v
...........................................\........\RISC_SPM.v
...........................................\........\test_RISC_SPM.v
...........................................\........\t_Bin_Cnt_Part_RTL_by_3.v
...........................................\........\uart8_rcvr.v
...........................................\........\uart8_rcvr_partition.v
...........................................\........\UART_xmtr_Arch.v
...........................................\ADDVB_Models_7.doc
...........................................\ADDVB_Models_7.v.txt
...........................................\Bin_Cnt_Part_RTL.v
...........................................\Bin_Cnt_Part_RTL_by_3.v
...........................................\Clock_Unit.v
...........................................\Gap_Finder.doc
...........................................\Gap_Finder.v
...........................................\RISC_SPM.v
...........................................\test_RISC_SPM.v
...........................................\t_Bin_Cnt_Part_RTL_by_3.v
...........................................\uart8_rcvr.v
...........................................\uart8_rcvr_partition.v
...........................................\UART_xmtr_Arch.v
...........................................\_vti_cnf
...........................................\........\ADDVB_Models_7.doc
...........................................\........\Bin_Cnt_Part_RTL.v
...........................................\........\Bin_Cnt_Part_RTL_by_3.v
...........................................\........\RISC_SPM.v
...........................................\........\test_RISC_SPM.v
...........................................\........\t_Bin_Cnt_Part_RTL_by_3.v
...........................................\........\uart8_rcvr.v
...........................................\........\uart8_rcvr_partition.v
...........................................\........\UART_xmtr_Arch.v