文件名称:expt12_10_phas
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基于fpga和sopc的用VHDL语言编写的EDA数字移相信号发生器-FPGA and SOPC based on the use of VHDL language shift EDA Digital Signal Generator
相关搜索： sopc
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下载文件列表
EXPT12_10_PHAS
..............\ADDER10B.VHD
..............\ADDER32B.VHD
..............\cmp_state.ini
..............\DATA
..............\....\LUT10X10.HEX
..............\....\LUT10X10.MIF
..............\db
..............\..\dds_vhdl.db_info
..............\..\dds_vhdl.project.hdb
..............\dds_vhdl.asm.rpt
..............\DDS_VHDL.CDF
..............\dds_vhdl.done
..............\dds_vhdl.fit.summary
..............\dds_vhdl.flow.rpt
..............\dds_vhdl.map.summary
..............\DDS_VHDL.PIN
..............\DDS_VHDL.QPF
..............\DDS_VHDL.QSF
..............\DDS_VHDL.QWS
..............\DDS_VHDL.SOF
..............\dds_vhdl.tan.summary
..............\DDS_VHDL.VHD
..............\dds_vhdl_assignment_defaults.qdf
..............\PLL20.VHD
..............\README
..............\......\GW48使用readme.txt
..............\REG10B.VHD
..............\REG32B.VHD
..............\SIN_ROM.VHD
..............\STP1.STP
..............\ADDER10B.VHD
..............\ADDER32B.VHD
..............\cmp_state.ini
..............\DATA
..............\....\LUT10X10.HEX
..............\....\LUT10X10.MIF
..............\db
..............\..\dds_vhdl.db_info
..............\..\dds_vhdl.project.hdb
..............\dds_vhdl.asm.rpt
..............\DDS_VHDL.CDF
..............\dds_vhdl.done
..............\dds_vhdl.fit.summary
..............\dds_vhdl.flow.rpt
..............\dds_vhdl.map.summary
..............\DDS_VHDL.PIN
..............\DDS_VHDL.QPF
..............\DDS_VHDL.QSF
..............\DDS_VHDL.QWS
..............\DDS_VHDL.SOF
..............\dds_vhdl.tan.summary
..............\DDS_VHDL.VHD
..............\dds_vhdl_assignment_defaults.qdf
..............\PLL20.VHD
..............\README
..............\......\GW48使用readme.txt
..............\REG10B.VHD
..............\REG32B.VHD
..............\SIN_ROM.VHD
..............\STP1.STP