文件名称:vga_lcd
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这个是VGA的核是NOIS开发时使用的IP CORES 在FPGA的开发中使用的比较多-This is a VGA Nois nuclear development is the use of IP CORES in the FPGA used in the development of more
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下载文件列表
vga_lcd
.......\bench
.......\.....\verilog
.......\.....\.......\sync_check.v
.......\.....\.......\tests.v
.......\.....\.......\test_bench_top.v
.......\.....\.......\wb_b3_check.v
.......\.....\.......\wb_mast_model.v
.......\.....\.......\wb_model_defines.v
.......\.....\.......\wb_slv_model.v
.......\doc
.......\...\src
.......\...\...\vga_core_enh.doc
.......\...\vga_core.pdf
.......\rtl
.......\...\verilog
.......\...\.......\generic_dpram.v
.......\...\.......\generic_spram.v
.......\...\.......\timescale.v
.......\...\.......\vga_clkgen.v
.......\...\.......\vga_colproc.v
.......\...\.......\vga_csm_pb.v
.......\...\.......\vga_curproc.v
.......\...\.......\vga_cur_cregs.v
.......\...\.......\vga_defines.v
.......\...\.......\vga_enh_top.v
.......\...\.......\vga_fifo.v
.......\...\.......\vga_fifo_dc.v
.......\...\.......\vga_pgen.v
.......\...\.......\vga_tgen.v
.......\...\.......\vga_vtim.v
.......\...\.......\vga_wb_master.v
.......\...\.......\vga_wb_slave.v
.......\...\vhdl
.......\...\....\colproc.vhd
.......\...\....\counter.vhd
.......\...\....\csm_pb.vhd
.......\...\....\dpm.vhd
.......\...\....\fifo.vhd
.......\...\....\fifo_dc.vhd
.......\...\....\pgen.vhd
.......\...\....\tgen.vhd
.......\...\....\vga.vhd
.......\...\....\vga_and_clut.vhd
.......\...\....\vga_and_clut_tstbench.vhd
.......\...\....\vtim.vhd
.......\...\....\wb_master.vhd
.......\...\....\wb_slave.vhd
.......\sim
.......\...\rtl_sim
.......\...\.......\bin
.......\...\.......\...\Makefile
.......\...\.......\run
.......\software
.......\........\drivers
.......\........\include
.......\........\.......\oc_vga_lcd.h
.......\syn
.......\...\bin
.......\...\...\comp.dc
.......\...\...\design_spec.dc
.......\...\...\lib_spec.dc
.......\...\...\read.dc
.......\...\log
.......\...\out
.......\...\run
.......\bench
.......\.....\verilog
.......\.....\.......\sync_check.v
.......\.....\.......\tests.v
.......\.....\.......\test_bench_top.v
.......\.....\.......\wb_b3_check.v
.......\.....\.......\wb_mast_model.v
.......\.....\.......\wb_model_defines.v
.......\.....\.......\wb_slv_model.v
.......\doc
.......\...\src
.......\...\...\vga_core_enh.doc
.......\...\vga_core.pdf
.......\rtl
.......\...\verilog
.......\...\.......\generic_dpram.v
.......\...\.......\generic_spram.v
.......\...\.......\timescale.v
.......\...\.......\vga_clkgen.v
.......\...\.......\vga_colproc.v
.......\...\.......\vga_csm_pb.v
.......\...\.......\vga_curproc.v
.......\...\.......\vga_cur_cregs.v
.......\...\.......\vga_defines.v
.......\...\.......\vga_enh_top.v
.......\...\.......\vga_fifo.v
.......\...\.......\vga_fifo_dc.v
.......\...\.......\vga_pgen.v
.......\...\.......\vga_tgen.v
.......\...\.......\vga_vtim.v
.......\...\.......\vga_wb_master.v
.......\...\.......\vga_wb_slave.v
.......\...\vhdl
.......\...\....\colproc.vhd
.......\...\....\counter.vhd
.......\...\....\csm_pb.vhd
.......\...\....\dpm.vhd
.......\...\....\fifo.vhd
.......\...\....\fifo_dc.vhd
.......\...\....\pgen.vhd
.......\...\....\tgen.vhd
.......\...\....\vga.vhd
.......\...\....\vga_and_clut.vhd
.......\...\....\vga_and_clut_tstbench.vhd
.......\...\....\vtim.vhd
.......\...\....\wb_master.vhd
.......\...\....\wb_slave.vhd
.......\sim
.......\...\rtl_sim
.......\...\.......\bin
.......\...\.......\...\Makefile
.......\...\.......\run
.......\software
.......\........\drivers
.......\........\include
.......\........\.......\oc_vga_lcd.h
.......\syn
.......\...\bin
.......\...\...\comp.dc
.......\...\...\design_spec.dc
.......\...\...\lib_spec.dc
.......\...\...\read.dc
.......\...\log
.......\...\out
.......\...\run