文件名称:testbench
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一个自己编写的全数字锁相环及其测试向量，比较简单但功能基本达到。-I have written an all-digital phase-locked loop and its test vectors, relatively simple to achieve but the basic function.
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下载文件列表
testbench
.........\ADPLL.cr.mti
.........\adpll.mpf
.........\ADPLL.v
.........\ADPLL.v.bak
.........\tb_adpll.acf
.........\tb_adpll.hif
.........\tb_ADPLL.v
.........\tb_ADPLL.v.bak
.........\vsim.wlf
.........\work
.........\....\@a@d@p@l@l
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\..........\_primary.vhd
.........\....\tb_@a@d@p@l@l
.........\....\.............\verilog.asm
.........\....\.............\_primary.dat
.........\....\.............\_primary.vhd
.........\....\_info
.........\ADPLL.cr.mti
.........\adpll.mpf
.........\ADPLL.v
.........\ADPLL.v.bak
.........\tb_adpll.acf
.........\tb_adpll.hif
.........\tb_ADPLL.v
.........\tb_ADPLL.v.bak
.........\vsim.wlf
.........\work
.........\....\@a@d@p@l@l
.........\....\..........\verilog.asm
.........\....\..........\_primary.dat
.........\....\..........\_primary.vhd
.........\....\tb_@a@d@p@l@l
.........\....\.............\verilog.asm
.........\....\.............\_primary.dat
.........\....\.............\_primary.vhd
.........\....\_info