文件名称:sine
介绍说明－－下载内容均来自于网络，请自行研究使用
用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
相关搜索： vhdl
正弦
quartus
verilog
sin
verilog
verilog
SINE
verilog_sine
0h
verilog
sin
lookup
table
source
code
sine
veril
Verilog
Generator
正弦
quartus
verilog
sin
verilog
verilog
SINE
verilog_sine
0h
verilog
sin
lookup
table
source
code
sine
veril
Verilog
Generator
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sine
....\default.cfg
....\default.cfg.bck
....\ROM.DAT
....\rom16x7.v
....\sgen.c
....\sim.vc
....\simv.daidir
....\...........\01j9_1.daidb
....\...........\3e3i_1.daidb
....\...........\vcs.dailu
....\...........\vcs_mstr.daidb
....\simv.exe
....\simv.exp
....\simv.lib
....\sine.v
....\sinetest.v
....\vcdplus.vpd
....\wave.bat
....\default.cfg
....\default.cfg.bck
....\ROM.DAT
....\rom16x7.v
....\sgen.c
....\sim.vc
....\simv.daidir
....\...........\01j9_1.daidb
....\...........\3e3i_1.daidb
....\...........\vcs.dailu
....\...........\vcs_mstr.daidb
....\simv.exe
....\simv.exp
....\simv.lib
....\sine.v
....\sinetest.v
....\vcdplus.vpd
....\wave.bat