文件名称:Chapter8Sample

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 127kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 玄*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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用FPGA实现的VGA/LCD显示的相关知识,包含了程序的主要结构和主要功能模块的实现过程-Using FPGA to achieve the VGA/LCD display relevant knowledge, including the procedures for the main structure and main function modules of the realization process
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Chapter8 Sample

...............\vga

...............\...\automake.log

...............\...\coregen.log

...............\...\coregen.prj

...............\...\generic_dpram.v

...............\...\generic_spram.v

...............\...\prjname.lso

...............\...\sync_check.v

...............\...\tests.v

...............\...\tests.v.bak

...............\...\test_bench_top.v

...............\...\test_bench_top.v.bak

...............\...\timescale.v

...............\...\vga.dhp

...............\...\vga.npl

...............\...\vga_clkgen.v

...............\...\vga_colproc.v

...............\...\vga_csm_pb.v

...............\...\vga_curproc.v

...............\...\vga_cur_cregs.v

...............\...\vga_defines.v

...............\...\vga_defines.v.bak

...............\...\vga_enh_top.cmd_log

...............\...\vga_enh_top.lso

...............\...\vga_enh_top.prj

...............\...\vga_enh_top.stx

...............\...\vga_enh_top.syr

...............\...\vga_enh_top.v

...............\...\vga_enh_top_vhdl.prj

...............\...\vga_fifo.v

...............\...\vga_fifo_dc.v

...............\...\vga_pgen.v

...............\...\vga_tgen.v

...............\...\vga_vtim.v

...............\...\vga_wb_master.v

...............\...\vga_wb_master.v.bak

...............\...\vga_wb_slave.v

...............\...\vga_wb_slave.v.bak

...............\...\wb_b3_check.v

...............\...\wb_b3_check.v.bak

...............\...\wb_mast_model.v

...............\...\wb_model_defines.v

...............\...\wb_model_defines.v.bak

...............\...\wb_slv_model.v

...............\...\wb_slv_model.v.bak

...............\...\xst

...............\...\...\work

...............\...\...\....\hdllib.ref

...............\...\...\....\vlg04

...............\...\...\....\.....\vga_wb_slave.bin

...............\...\...\....\vlg05

...............\...\...\....\.....\vga_wb_master.bin

...............\...\...\....\vlg07

...............\...\...\....\.....\vga_fifo_dc.bin

...............\...\...\....\.....\vga_pgen.bin

...............\...\...\....\vlg34

...............\...\...\....\.....\generic_dpram.bin

...............\...\...\....\vlg4D

...............\...\...\....\.....\vga_csm_pb.bin

...............\...\...\....\.....\vga_vtim.bin

...............\...\...\....\vlg53

...............\...\...\....\.....\generic_spram.bin

...............\...\...\....\vlg59

...............\...\...\....\.....\vga_clkgen.bin

...............\...\...\....\vlg5D

...............\...\...\....\.....\vga_fifo.bin

...............\...\...\....\vlg5F

...............\...\...\....\.....\vga_colproc.bin

...............\...\...\....\vlg6A

...............\...\...\....\.....\vga_enh_top.bin

...............\...\...\....\vlg7B

...............\...\...\....\.....\vga_tgen.bin

...............\...\__projnav

...............\...\.........\coregen.rsp

...............\...\.........\runXst_tcl.rsp

...............\...\.........\vga.gfl

...............\...\.........\vga_enh_top.xst

...............\...\.........\vga_flowplus.gfl

...............\...\.........\xst_sprjTOstx_tcl.rsp

...............\...\__projnav.log

...............\使用说明.txt

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