文件名称:uart_regs
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此程序为串行通信程序,采用verilog语言编写的,经过仿真验证已经通过.-This procedure for the serial communication procedures, the use of Verilog language, after simulation has been adopted.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart_regs
.........\core
.........\....\db
.........\....\myfifo_10.v
.........\....\myfifo_10_bb.v
.........\....\myfifo_10_waveforms.html
.........\....\myfifo_8.v
.........\....\myfifo_8_bb.v
.........\....\myfifo_8_waveforms.html
.........\dev
.........\...\chip_editor.acv
.........\...\cmp_state.ini
.........\...\db
.........\...\..\add_sub_1jh.tdf
.........\...\..\add_sub_dhh.tdf
.........\...\..\add_sub_ehh.tdf
.........\...\..\add_sub_fhh.tdf
.........\...\..\add_sub_ihh.tdf
.........\...\..\add_sub_rih.tdf
.........\...\..\altsyncram_4pl1.tdf
.........\...\..\altsyncram_apb1.tdf
.........\...\..\altsyncram_gml1.tdf
.........\...\..\altsyncram_mmb1.tdf
.........\...\..\a_dpfifo_4nl.tdf
.........\...\..\a_dpfifo_lh81.tdf
.........\...\..\a_dpfifo_rll.tdf
.........\...\..\a_dpfifo_ui81.tdf
.........\...\..\a_fefifo_66f.tdf
.........\...\..\a_fefifo_qve.tdf
.........\...\..\cntr_9d7.tdf
.........\...\..\cntr_tcb.tdf
.........\...\..\dpram_2h51.tdf
.........\...\..\dpram_81k.tdf
.........\...\..\dpram_h2k.tdf
.........\...\..\dpram_pf51.tdf
.........\...\..\prev_cmp_uart_regs.map.qmsg
.........\...\..\scfifo_eaq.tdf
.........\...\..\scfifo_eb81.tdf
.........\...\..\scfifo_nbq.tdf
.........\...\..\scfifo_nc81.tdf
.........\...\..\uart_regs-sim.vwf
.........\...\..\uart_regs.cbx.xml
.........\...\..\uart_regs.cmp.rdb
.........\...\..\uart_regs.dbp
.........\...\..\uart_regs.db_info
.........\...\..\uart_regs.eco.cdb
.........\...\..\uart_regs.hier_info
.........\...\..\uart_regs.hif
.........\...\..\uart_regs.map.cdb
.........\...\..\uart_regs.map.hdb
.........\...\..\uart_regs.map.logdb
.........\...\..\uart_regs.map.qmsg
.........\...\..\uart_regs.pre_map.cdb
.........\...\..\uart_regs.pre_map.hdb
.........\...\..\uart_regs.psp
.........\...\..\uart_regs.pss
.........\...\..\uart_regs.rtlv.hdb
.........\...\..\uart_regs.rtlv_sg.cdb
.........\...\..\uart_regs.rtlv_sg_swap.cdb
.........\...\..\uart_regs.sgdiff.cdb
.........\...\..\uart_regs.sgdiff.hdb
.........\...\..\uart_regs.sld_design_entry.sci
.........\...\..\uart_regs.sld_design_entry_dsc.sci
.........\...\..\uart_regs.syn_hier_info
.........\...\..\uart_regs_cmp.qrpt
.........\...\..\uart_regs_hier_info
.........\...\..\uart_regs_sim.qrpt
.........\...\..\uart_regs_syn_hier_info
.........\...\..\wed.wsf
.........\...\prev_cmp_uart_regs.qmsg
.........\...\sim.cfg
.........\...\sopc_builder_log.txt
.........\...\uart_regs.asm.rpt
.........\...\uart_regs.done
.........\...\uart_regs.dpf
.........\...\uart_regs.fit.eqn
.........\...\uart_regs.fit.rpt
.........\...\uart_regs.fld
.........\...\uart_regs.flow.rpt
.........\...\uart_regs.map.eqn
.........\...\uart_regs.map.rpt
.........\...\uart_regs.map.smsg
.........\...\uart_regs.map.summary
.........\...\uart_regs.pin
.........\...\uart_regs.pof
.........\...\uart_regs.qpf
.........\...\uart_regs.qsf
.........\...\uart_regs.qws
.........\...\uart_regs.rbf
.........\...\uart_regs.sim.rpt
.........\...\uart_regs.sof
.........\...\uart_regs.tan.rpt
.........\...\uart_regs.tan.summary
.........\...\uart_regs_assignment_defaults.qdf
.........\sim
.........\...\funcsim
.........\...\.......\uart_regs_h.vwf
.........\...\.......\uart_regs_pre.vwf
.........\core
.........\....\db
.........\....\myfifo_10.v
.........\....\myfifo_10_bb.v
.........\....\myfifo_10_waveforms.html
.........\....\myfifo_8.v
.........\....\myfifo_8_bb.v
.........\....\myfifo_8_waveforms.html
.........\dev
.........\...\chip_editor.acv
.........\...\cmp_state.ini
.........\...\db
.........\...\..\add_sub_1jh.tdf
.........\...\..\add_sub_dhh.tdf
.........\...\..\add_sub_ehh.tdf
.........\...\..\add_sub_fhh.tdf
.........\...\..\add_sub_ihh.tdf
.........\...\..\add_sub_rih.tdf
.........\...\..\altsyncram_4pl1.tdf
.........\...\..\altsyncram_apb1.tdf
.........\...\..\altsyncram_gml1.tdf
.........\...\..\altsyncram_mmb1.tdf
.........\...\..\a_dpfifo_4nl.tdf
.........\...\..\a_dpfifo_lh81.tdf
.........\...\..\a_dpfifo_rll.tdf
.........\...\..\a_dpfifo_ui81.tdf
.........\...\..\a_fefifo_66f.tdf
.........\...\..\a_fefifo_qve.tdf
.........\...\..\cntr_9d7.tdf
.........\...\..\cntr_tcb.tdf
.........\...\..\dpram_2h51.tdf
.........\...\..\dpram_81k.tdf
.........\...\..\dpram_h2k.tdf
.........\...\..\dpram_pf51.tdf
.........\...\..\prev_cmp_uart_regs.map.qmsg
.........\...\..\scfifo_eaq.tdf
.........\...\..\scfifo_eb81.tdf
.........\...\..\scfifo_nbq.tdf
.........\...\..\scfifo_nc81.tdf
.........\...\..\uart_regs-sim.vwf
.........\...\..\uart_regs.cbx.xml
.........\...\..\uart_regs.cmp.rdb
.........\...\..\uart_regs.dbp
.........\...\..\uart_regs.db_info
.........\...\..\uart_regs.eco.cdb
.........\...\..\uart_regs.hier_info
.........\...\..\uart_regs.hif
.........\...\..\uart_regs.map.cdb
.........\...\..\uart_regs.map.hdb
.........\...\..\uart_regs.map.logdb
.........\...\..\uart_regs.map.qmsg
.........\...\..\uart_regs.pre_map.cdb
.........\...\..\uart_regs.pre_map.hdb
.........\...\..\uart_regs.psp
.........\...\..\uart_regs.pss
.........\...\..\uart_regs.rtlv.hdb
.........\...\..\uart_regs.rtlv_sg.cdb
.........\...\..\uart_regs.rtlv_sg_swap.cdb
.........\...\..\uart_regs.sgdiff.cdb
.........\...\..\uart_regs.sgdiff.hdb
.........\...\..\uart_regs.sld_design_entry.sci
.........\...\..\uart_regs.sld_design_entry_dsc.sci
.........\...\..\uart_regs.syn_hier_info
.........\...\..\uart_regs_cmp.qrpt
.........\...\..\uart_regs_hier_info
.........\...\..\uart_regs_sim.qrpt
.........\...\..\uart_regs_syn_hier_info
.........\...\..\wed.wsf
.........\...\prev_cmp_uart_regs.qmsg
.........\...\sim.cfg
.........\...\sopc_builder_log.txt
.........\...\uart_regs.asm.rpt
.........\...\uart_regs.done
.........\...\uart_regs.dpf
.........\...\uart_regs.fit.eqn
.........\...\uart_regs.fit.rpt
.........\...\uart_regs.fld
.........\...\uart_regs.flow.rpt
.........\...\uart_regs.map.eqn
.........\...\uart_regs.map.rpt
.........\...\uart_regs.map.smsg
.........\...\uart_regs.map.summary
.........\...\uart_regs.pin
.........\...\uart_regs.pof
.........\...\uart_regs.qpf
.........\...\uart_regs.qsf
.........\...\uart_regs.qws
.........\...\uart_regs.rbf
.........\...\uart_regs.sim.rpt
.........\...\uart_regs.sof
.........\...\uart_regs.tan.rpt
.........\...\uart_regs.tan.summary
.........\...\uart_regs_assignment_defaults.qdf
.........\sim
.........\...\funcsim
.........\...\.......\uart_regs_h.vwf
.........\...\.......\uart_regs_pre.vwf