文件名称:cpu
介绍说明－－下载内容均来自于网络，请自行研究使用
本人制作的8位CPU,有简单的加减,输入,输出操作,希望大家好用-I produced eight CPU, has a simple addition and subtraction, input and output operations, I hope everyone use
相关搜索： 8位cpu
(系统自动生成,下载前可以参看下载内容)
下载文件列表
80386.zip
8051core-Verilog.zip
8088verilog.zip
8088vhdl.zip
IT51_src[1].tar.gz
openrisc1200
............\or1k
............\....\or1200
............\....\......\bench
............\....\......\.....\CVS
............\....\......\.....\...\Entries
............\....\......\.....\...\Repository
............\....\......\.....\...\Root
............\....\......\.....\README
............\....\......\CVS
............\....\......\...\Entries
............\....\......\...\Repository
............\....\......\...\Root
............\....\......\doc
............\....\......\...\CVS
............\....\......\...\...\Entries
............\....\......\...\...\Repository
............\....\......\...\...\Root
............\....\......\...\or1200_spec.doc
............\....\......\...\or1200_spec.pdf
............\....\......\lib
............\....\......\...\CVS
............\....\......\...\...\Entries
............\....\......\...\...\Repository
............\....\......\...\...\Root
............\....\......\...\README
............\....\......\lint
............\....\......\....\bin
............\....\......\....\...\CVS
............\....\......\....\...\...\Entries
............\....\......\....\...\...\Repository
............\....\......\....\...\...\Root
............\....\......\....\...\README
............\....\......\....\...\run_lint
............\....\......\....\CVS
............\....\......\....\...\Entries
............\....\......\....\...\Repository
............\....\......\....\...\Root
............\....\......\....\log
............\....\......\....\...\CVS
............\....\......\....\...\...\Entries
............\....\......\....\...\...\Repository
............\....\......\....\...\...\Root
............\....\......\....\...\README
............\....\......\....\run
............\....\......\....\...\CVS
............\....\......\....\...\...\Entries
............\....\......\....\...\...\Repository
............\....\......\....\...\...\Root
............\....\......\....\...\README
............\....\......\rtl
............\....\......\...\CVS
............\....\......\...\...\Entries
............\....\......\...\...\Repository
............\....\......\...\...\Root
............\....\......\...\verilog
............\....\......\...\.......\CVS
............\....\......\...\.......\...\Entries
............\....\......\...\.......\...\Repository
............\....\......\...\.......\...\Root
............\....\......\...\.......\or1200_alu.v
............\....\......\...\.......\or1200_amultp2_32x32.v
............\....\......\...\.......\or1200_cfgr.v
............\....\......\...\.......\or1200_cpu.v
............\....\......\...\.......\or1200_ctrl.v
............\....\......\...\.......\or1200_dc_fsm.v
............\....\......\...\.......\or1200_dc_ram.v
............\....\......\...\.......\or1200_dc_tag.v
............\....\......\...\.......\or1200_dc_top.v
............\....\......\...\.......\or1200_defines.v
............\....\......\...\.......\or1200_dmmu_tlb.v
............\....\......\...\.......\or1200_dmmu_top.v
............\....\......\...\.......\or1200_dpram_256x32.v
............\....\......\...\.......\or1200_dpram_32x32.v
............\....\......\...\.......\or1200_du.v
............\....\......\...\.......\or1200_except.v
............\....\......\...\.......\or1200_freeze.v
............\....\......\...\.......\or1200_genpc.v
............\....\......\...\.......\or1200_gmultp2_32x32.v
............\....\......\...\.......\or1200_ic_fsm.v
............\....\......\...\.......\or1200_ic_ram.v
............\....\......\...\.......\or1200_ic_tag.v
............\....\......\...\.......\or1200_ic_top.v
............\....\......\...\.......\or1200_if.v
............\....\......\...\.......\or1200_immu_tlb.v
............\....\......\...\.......\or1200_immu_top.v
............\....\......\...\.......\or1200_iwb_biu.v
............\....\......\...\.......\or1200_lsu.v
............\....\......\...\.......\or1200_mem2reg.v
............\....\......\...\.......\or1200_mult_mac.v
............\....\......\...\.......\or1200_operandmuxes.v
............\....\......\...\..
8051core-Verilog.zip
8088verilog.zip
8088vhdl.zip
IT51_src[1].tar.gz
openrisc1200
............\or1k
............\....\or1200
............\....\......\bench
............\....\......\.....\CVS
............\....\......\.....\...\Entries
............\....\......\.....\...\Repository
............\....\......\.....\...\Root
............\....\......\.....\README
............\....\......\CVS
............\....\......\...\Entries
............\....\......\...\Repository
............\....\......\...\Root
............\....\......\doc
............\....\......\...\CVS
............\....\......\...\...\Entries
............\....\......\...\...\Repository
............\....\......\...\...\Root
............\....\......\...\or1200_spec.doc
............\....\......\...\or1200_spec.pdf
............\....\......\lib
............\....\......\...\CVS
............\....\......\...\...\Entries
............\....\......\...\...\Repository
............\....\......\...\...\Root
............\....\......\...\README
............\....\......\lint
............\....\......\....\bin
............\....\......\....\...\CVS
............\....\......\....\...\...\Entries
............\....\......\....\...\...\Repository
............\....\......\....\...\...\Root
............\....\......\....\...\README
............\....\......\....\...\run_lint
............\....\......\....\CVS
............\....\......\....\...\Entries
............\....\......\....\...\Repository
............\....\......\....\...\Root
............\....\......\....\log
............\....\......\....\...\CVS
............\....\......\....\...\...\Entries
............\....\......\....\...\...\Repository
............\....\......\....\...\...\Root
............\....\......\....\...\README
............\....\......\....\run
............\....\......\....\...\CVS
............\....\......\....\...\...\Entries
............\....\......\....\...\...\Repository
............\....\......\....\...\...\Root
............\....\......\....\...\README
............\....\......\rtl
............\....\......\...\CVS
............\....\......\...\...\Entries
............\....\......\...\...\Repository
............\....\......\...\...\Root
............\....\......\...\verilog
............\....\......\...\.......\CVS
............\....\......\...\.......\...\Entries
............\....\......\...\.......\...\Repository
............\....\......\...\.......\...\Root
............\....\......\...\.......\or1200_alu.v
............\....\......\...\.......\or1200_amultp2_32x32.v
............\....\......\...\.......\or1200_cfgr.v
............\....\......\...\.......\or1200_cpu.v
............\....\......\...\.......\or1200_ctrl.v
............\....\......\...\.......\or1200_dc_fsm.v
............\....\......\...\.......\or1200_dc_ram.v
............\....\......\...\.......\or1200_dc_tag.v
............\....\......\...\.......\or1200_dc_top.v
............\....\......\...\.......\or1200_defines.v
............\....\......\...\.......\or1200_dmmu_tlb.v
............\....\......\...\.......\or1200_dmmu_top.v
............\....\......\...\.......\or1200_dpram_256x32.v
............\....\......\...\.......\or1200_dpram_32x32.v
............\....\......\...\.......\or1200_du.v
............\....\......\...\.......\or1200_except.v
............\....\......\...\.......\or1200_freeze.v
............\....\......\...\.......\or1200_genpc.v
............\....\......\...\.......\or1200_gmultp2_32x32.v
............\....\......\...\.......\or1200_ic_fsm.v
............\....\......\...\.......\or1200_ic_ram.v
............\....\......\...\.......\or1200_ic_tag.v
............\....\......\...\.......\or1200_ic_top.v
............\....\......\...\.......\or1200_if.v
............\....\......\...\.......\or1200_immu_tlb.v
............\....\......\...\.......\or1200_immu_top.v
............\....\......\...\.......\or1200_iwb_biu.v
............\....\......\...\.......\or1200_lsu.v
............\....\......\...\.......\or1200_mem2reg.v
............\....\......\...\.......\or1200_mult_mac.v
............\....\......\...\.......\or1200_operandmuxes.v
............\....\......\...\..