eco_tutorial

............\db

............\..\eco_implemented.db

............\..\eco_optimized.db

............\..\eco_recycled.db

............\..\new_hdl.db

............\..\new_netlist.db

............\..\old_hdl.db

............\..\old_netlist.db

............\..\old_net_u.db

............\README

............\reports

............\scripts

............\.......\create_db.scr

............\.......\eco.script

............\.......\spare_cell

............\.......\uwave_ctl.pdef

............\src

............\...\nu_uwave.v

............\...\nu_uwave.vhd

............\...\uwave.v

............\...\uwave.vhd

............\work

examples

........\bc_view

........\.......\verilog

........\.......\.......\db

........\.......\.......\..\example.db

........\.......\.......\example.proj

........\.......\.......\hdl

........\.......\.......\...\example.v

........\.......\.......\...\mult_proc.v

........\.......\.......\mult_proc.scr

........\.......\.......\rams

........\.......\.......\....\cs_rams.sl

........\.......\.......\....\cs_rams.sldb

........\.......\.......\reports

........\.......\.......\.......\example.rpt

........\.......\.......\scr

........\.......\.......\...\example.scr

........\.......\.......\soln

........\.......\.......\....\mult_proc.v

........\.......\.......\work

........\.......\.......\....\example%verilog.syn

........\.......\.......\....\example%verilog__verilog.syn

........\.......\.......\....\EXAMPLE.mr

........\.......\.......\....\example.v.bi

........\.......\.......\....\example.v.id

........\.......\vhdl

........\.......\....\db

........\.......\....\..\example.db

........\.......\....\example.proj

........\.......\....\hdl

........\.......\....\...\example.vhd

........\.......\....\...\mult_proc.vhd

........\.......\....\mult_proc.scr

........\.......\....\rams

........\.......\....\....\cs_rams.sl

........\.......\....\....\cs_rams.sldb

........\.......\....\reports

........\.......\....\.......\example.rpt

........\.......\....\scr

........\.......\....\...\example.scr

........\.......\....\soln

........\.......\....\....\mult_proc.vhd

........\.......\....\work

........\.......\....\....\EXAMPLE.mr

........\.......\....\....\EXAMPLE.st

........\.......\....\....\EXAMPLE.syn

........\.......\....\....\example.vhd.bi

........\.......\....\....\example.vhd.id

........\.......\....\....\EXAMPLE__BEHAVIORAL.st

........\.......\....\....\EXAMPLE__BEHAVIORAL.syn

........\dotfiles

........\........\cshrc

........\........\nm_rules.dcsh

........\........\synopsys

........\........\Xdefaults

........\fsm

........\...\proc2.db

........\...\proc2.v

........\...\proc2.vhd

........\...\proc3.db

........\...\proc3.v

........\...\proc3.vhd

........\...\proc4.db

........\...\proc4.v

........\...\proc4.vhd

........\...\work

........\README

........\rtl_analyzer

........\............\verilog

........\............\.......\clean

........\............\.......\gtech

........\............\.......\.....\addr_combo.ra

........\............\.......\.....\addr_combo.v.bi

........\............\.......\.....\addr_combo.v.id

........\............\.......\.....\addr_fsm.ra

........\............\.......\.....\addr_fsm.v.bi

........\............\.......\.....\addr_fsm.v.id