5k_preset

.........\Verilog

.........\.......\.synopsys_dc.setup

.........\.......\command.log

.........\.......\dc2ncf.log

.........\.......\M1_files

.........\.......\........\command.his

.........\.......\........\map.mrp

.........\.......\........\map.ncd

.........\.......\........\map.ngm

.........\.......\........\map.pcf

.........\.......\........\netlist.lst

.........\.......\........\ngdbuild.log

.........\.......\........\preset_5k.bgn

.........\.......\........\preset_5k.bit

.........\.......\........\preset_5k.bld

.........\.......\........\preset_5k.dly

.........\.......\........\preset_5k.drc

.........\.......\........\preset_5k.ncd

.........\.......\........\preset_5k.ncf

.........\.......\........\preset_5k.ngd

.........\.......\........\preset_5k.ngo

.........\.......\........\preset_5k.pad

.........\.......\........\preset_5k.par

.........\.......\........\preset_5k.pcf

.........\.......\........\preset_5k.sxnf

.........\.......\........\preset_5k.twr

.........\.......\........\time_sim.alf

.........\.......\........\time_sim.nga

.........\.......\........\time_sim.pin

.........\.......\........\time_sim.sdf

.........\.......\........\time_sim.tv

.........\.......\........\time_sim.v

.........\.......\preset_5k.db

.........\.......\preset_5k.dc

.........\.......\preset_5k.fpga

.........\.......\preset_5k.log

.........\.......\preset_5k.ncf

.........\.......\preset_5k.script

.........\.......\preset_5k.sxnf

.........\.......\preset_5k.timing

.........\.......\preset_5k.v

.........\VHDL

.........\....\.synopsys_dc.setup

.........\....\command.log

.........\....\dc2ncf.log

.........\....\M1_files

.........\....\........\command.his

.........\....\........\map.mrp

.........\....\........\map.ncd

.........\....\........\map.ngm

.........\....\........\map.pcf

.........\....\........\netlist.lst

.........\....\........\ngdbuild.log

.........\....\........\preset_5k.bgn

.........\....\........\preset_5k.bit

.........\....\........\preset_5k.bld

.........\....\........\preset_5k.dly

.........\....\........\preset_5k.drc

.........\....\........\preset_5k.ncd

.........\....\........\preset_5k.ncf

.........\....\........\preset_5k.ngd

.........\....\........\preset_5k.ngo

.........\....\........\preset_5k.pad

.........\....\........\preset_5k.par

.........\....\........\preset_5k.pcf

.........\....\........\preset_5k.sxnf

.........\....\........\preset_5k.twr

.........\....\........\time_sim.alf

.........\....\........\time_sim.nga

.........\....\........\time_sim.sdf

.........\....\........\time_sim.vhd

.........\....\preset_5k.db

.........\....\preset_5k.dc

.........\....\preset_5k.fpga

.........\....\preset_5k.log

.........\....\preset_5k.ncf

.........\....\preset_5k.script

.........\....\preset_5k.sxnf

.........\....\preset_5k.timing

.........\....\preset_5k.vhd

.........\....\WORK

.........\....\....\PRESET_5K.mra

.........\....\....\PRESET_5K.sim

.........\....\....\PRESET_5K.syn

.........\....\....\PRESET_5K__BEHAV.sim

.........\....\....\PRESET_5K__BEHAV.syn

Barrel_SR

.........\Verilog

.........\.......\.synopsys_dc.setup

.........\.......\Barrel

.........\.......\......\.synopsys_dc.setup

.........\.......\......\barrel.db

.........\.......\......\barrel.dc

.........\.......\......\barrel.fpga

.........\.......\......\barrel.log

.........\.......\......\barrel.ncf

.........\.......\......\barrel.script

.........\.......\......\barrel.sxnf

.........\.......\......\barrel.timing