文件名称:DE2_TV_m_write
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DE2_TV_m_write.rar是用来去处抖动的，我使用它是在我做基于FPGA的字符识别技术时用到的-DE2_TV_m_write.rar jitter is used to place, and I use it when I make the character recognition based on FPGA technology used
相关搜索： 字符识别
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下载文件列表
DE2_TV_m_write
..............\AUDIO_DAC.v
..............\avl_m_w.bsf
..............\avl_m_w.ptf
..............\avl_m_w.v
..............\avl_m_w_generation_script
..............\avl_m_w_log.txt
..............\avl_m_w_setup_quartus.tcl
..............\avl_m_w_sim
..............\...........\atail-f.pl
..............\...........\avl_m_w_sim.mpf
..............\...........\contents_file_warning.txt
..............\...........\cpu_0_bht_ram.dat
..............\...........\cpu_0_bht_ram.hex
..............\...........\cpu_0_dc_tag_ram.dat
..............\...........\cpu_0_dc_tag_ram.hex
..............\...........\cpu_0_ic_tag_ram.dat
..............\...........\cpu_0_ic_tag_ram.hex
..............\...........\cpu_0_ociram_default_contents.dat
..............\...........\cpu_0_ociram_default_contents.hex
..............\...........\cpu_0_rf_ram_a.dat
..............\...........\cpu_0_rf_ram_a.hex
..............\...........\cpu_0_rf_ram_b.dat
..............\...........\cpu_0_rf_ram_b.hex
..............\...........\create_avl_m_w_project.do
..............\...........\jtag_uart_0_input_mutex.dat
..............\...........\jtag_uart_0_input_stream.dat
..............\...........\jtag_uart_0_log.bat
..............\...........\jtag_uart_0_output_stream.dat
..............\...........\list_presets.do
..............\...........\modelsim.tcl
..............\...........\sdram_0.dat
..............\...........\setup_sim.do
..............\...........\transcript
..............\...........\virtuals.do
..............\...........\wave_presets.do
..............\...........\work
..............\...........\....\_info
..............\ce_temp_directory
..............\cpu_0.v
..............\cpu_0_bht_ram.mif
..............\cpu_0_dc_tag_ram.mif
..............\cpu_0_ic_tag_ram.mif
..............\cpu_0_jtag_debug_module.v
..............\cpu_0_jtag_debug_module_wrapper.v
..............\cpu_0_mult_cell.v
..............\cpu_0_ociram_default_contents.mif
..............\cpu_0_rf_ram_a.mif
..............\cpu_0_rf_ram_b.mif
..............\cpu_0_test_bench.v
..............\db
..............\..\add_sub_lkc.tdf
..............\..\add_sub_mkc.tdf
..............\..\altsyncram_04l1.tdf
..............\..\altsyncram_1cm2.tdf
..............\..\altsyncram_2cm2.tdf
..............\..\altsyncram_3cm2.tdf
..............\..\altsyncram_52f1.tdf
..............\..\altsyncram_5bm2.tdf
..............\..\altsyncram_6c32.tdf
..............\..\altsyncram_a682.tdf
..............\..\altsyncram_amh1.tdf
..............\..\altsyncram_br41.tdf
..............\..\altsyncram_ckb2.tdf
..............\..\altsyncram_d2i1.tdf
..............\..\altsyncram_drg1.tdf
..............\..\altsyncram_e4l1.tdf
..............\..\altsyncram_ft52.tdf
..............\..\altsyncram_g4l1.tdf
..............\..\altsyncram_irg2.tdf
..............\..\altsyncram_jbm2.tdf
..............\..\altsyncram_jk61.tdf
..............\..\altsyncram_k1l1.tdf
..............\..\altsyncram_k4l1.tdf
..............\..\altsyncram_kn21.tdf
..............\..\altsyncram_koh1.tdf
..............\..\altsyncram_lbm2.tdf
..............\..\altsyncram_loh1.tdf
..............\..\altsyncram_m4l1.tdf
..............\..\altsyncram_pap1.tdf
..............\..\altsyncram_pbm2.tdf
..............\..\altsyncram_pfn1.tdf
..............\..\altsyncram_q0c1.tdf
..............\..\altsyncram_q4l1.tdf
..............\..\altsyncram_qh52.tdf
..............\..\altsyncram_rbm2.tdf
..............\..\altsyncram_s4l1.tdf
..............\..\altsyncram_sbf1.tdf
..............\..\altsyncram_sia2.tdf
..............\..\altsyncram_t4l1.tdf
..............\..\altsyncram_u4l1.tdf
..............\..\altsyncram_ui32.tdf
..............\..\altsyncram_vbm2.tdf
..............\..\alt_synch_pipe_0e8.tdf
..............\..\alt_synch_pipe_1e8.tdf
..............\..\alt_synch_pipe_2e8.tdf
..............\..\alt_synch_pipe_vd8.tdf
..............\..\alt_u_div_7qg.tdf
..............\..\alt_u_div_e5f.tdf
..............\..\a_dpfifo_oa61.tdf
..............\AUDIO_DAC.v
..............\avl_m_w.bsf
..............\avl_m_w.ptf
..............\avl_m_w.v
..............\avl_m_w_generation_script
..............\avl_m_w_log.txt
..............\avl_m_w_setup_quartus.tcl
..............\avl_m_w_sim
..............\...........\atail-f.pl
..............\...........\avl_m_w_sim.mpf
..............\...........\contents_file_warning.txt
..............\...........\cpu_0_bht_ram.dat
..............\...........\cpu_0_bht_ram.hex
..............\...........\cpu_0_dc_tag_ram.dat
..............\...........\cpu_0_dc_tag_ram.hex
..............\...........\cpu_0_ic_tag_ram.dat
..............\...........\cpu_0_ic_tag_ram.hex
..............\...........\cpu_0_ociram_default_contents.dat
..............\...........\cpu_0_ociram_default_contents.hex
..............\...........\cpu_0_rf_ram_a.dat
..............\...........\cpu_0_rf_ram_a.hex
..............\...........\cpu_0_rf_ram_b.dat
..............\...........\cpu_0_rf_ram_b.hex
..............\...........\create_avl_m_w_project.do
..............\...........\jtag_uart_0_input_mutex.dat
..............\...........\jtag_uart_0_input_stream.dat
..............\...........\jtag_uart_0_log.bat
..............\...........\jtag_uart_0_output_stream.dat
..............\...........\list_presets.do
..............\...........\modelsim.tcl
..............\...........\sdram_0.dat
..............\...........\setup_sim.do
..............\...........\transcript
..............\...........\virtuals.do
..............\...........\wave_presets.do
..............\...........\work
..............\...........\....\_info
..............\ce_temp_directory
..............\cpu_0.v
..............\cpu_0_bht_ram.mif
..............\cpu_0_dc_tag_ram.mif
..............\cpu_0_ic_tag_ram.mif
..............\cpu_0_jtag_debug_module.v
..............\cpu_0_jtag_debug_module_wrapper.v
..............\cpu_0_mult_cell.v
..............\cpu_0_ociram_default_contents.mif
..............\cpu_0_rf_ram_a.mif
..............\cpu_0_rf_ram_b.mif
..............\cpu_0_test_bench.v
..............\db
..............\..\add_sub_lkc.tdf
..............\..\add_sub_mkc.tdf
..............\..\altsyncram_04l1.tdf
..............\..\altsyncram_1cm2.tdf
..............\..\altsyncram_2cm2.tdf
..............\..\altsyncram_3cm2.tdf
..............\..\altsyncram_52f1.tdf
..............\..\altsyncram_5bm2.tdf
..............\..\altsyncram_6c32.tdf
..............\..\altsyncram_a682.tdf
..............\..\altsyncram_amh1.tdf
..............\..\altsyncram_br41.tdf
..............\..\altsyncram_ckb2.tdf
..............\..\altsyncram_d2i1.tdf
..............\..\altsyncram_drg1.tdf
..............\..\altsyncram_e4l1.tdf
..............\..\altsyncram_ft52.tdf
..............\..\altsyncram_g4l1.tdf
..............\..\altsyncram_irg2.tdf
..............\..\altsyncram_jbm2.tdf
..............\..\altsyncram_jk61.tdf
..............\..\altsyncram_k1l1.tdf
..............\..\altsyncram_k4l1.tdf
..............\..\altsyncram_kn21.tdf
..............\..\altsyncram_koh1.tdf
..............\..\altsyncram_lbm2.tdf
..............\..\altsyncram_loh1.tdf
..............\..\altsyncram_m4l1.tdf
..............\..\altsyncram_pap1.tdf
..............\..\altsyncram_pbm2.tdf
..............\..\altsyncram_pfn1.tdf
..............\..\altsyncram_q0c1.tdf
..............\..\altsyncram_q4l1.tdf
..............\..\altsyncram_qh52.tdf
..............\..\altsyncram_rbm2.tdf
..............\..\altsyncram_s4l1.tdf
..............\..\altsyncram_sbf1.tdf
..............\..\altsyncram_sia2.tdf
..............\..\altsyncram_t4l1.tdf
..............\..\altsyncram_u4l1.tdf
..............\..\altsyncram_ui32.tdf
..............\..\altsyncram_vbm2.tdf
..............\..\alt_synch_pipe_0e8.tdf
..............\..\alt_synch_pipe_1e8.tdf
..............\..\alt_synch_pipe_2e8.tdf
..............\..\alt_synch_pipe_vd8.tdf
..............\..\alt_u_div_7qg.tdf
..............\..\alt_u_div_e5f.tdf
..............\..\a_dpfifo_oa61.tdf