文件名称:Lab1_FPGA
介绍说明－－下载内容均来自于网络，请自行研究使用
lab1——FPGA这个文件中体统了如何如何使用verilog Hdl以及如何使其在FPGA开发板上实现-lab1- FPGA decency in this document on how to how to use the verilog Hdl and how to make it realize in FPGA development board
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Lab1_FPGA
.........\db
.........\..\Lab1.asm.qmsg
.........\..\Lab1.cbx.xml
.........\..\Lab1.cmp.bpm
.........\..\Lab1.cmp.cdb
.........\..\Lab1.cmp.ecobp
.........\..\Lab1.cmp.hdb
.........\..\Lab1.cmp.logdb
.........\..\Lab1.cmp.rdb
.........\..\Lab1.cmp.tdb
.........\..\Lab1.cmp0.ddb
.........\..\Lab1.cmp_bb.cdb
.........\..\Lab1.cmp_bb.hdb
.........\..\Lab1.cmp_bb.logdb
.........\..\Lab1.cmp_bb.rcf
.........\..\Lab1.dbp
.........\..\Lab1.db_info
.........\..\Lab1.eco.cdb
.........\..\Lab1.fit.qmsg
.........\..\Lab1.hier_info
.........\..\Lab1.hif
.........\..\Lab1.map.bpm
.........\..\Lab1.map.cdb
.........\..\Lab1.map.ecobp
.........\..\Lab1.map.hdb
.........\..\Lab1.map.logdb
.........\..\Lab1.map.qmsg
.........\..\Lab1.map_bb.cdb
.........\..\Lab1.map_bb.hdb
.........\..\Lab1.map_bb.logdb
.........\..\Lab1.pre_map.cdb
.........\..\Lab1.pre_map.hdb
.........\..\Lab1.psp
.........\..\Lab1.pss
.........\..\Lab1.rtlv.hdb
.........\..\Lab1.rtlv_sg.cdb
.........\..\Lab1.rtlv_sg_swap.cdb
.........\..\Lab1.sgdiff.cdb
.........\..\Lab1.sgdiff.hdb
.........\..\Lab1.signalprobe.cdb
.........\..\Lab1.sld_design_entry.sci
.........\..\Lab1.sld_design_entry_dsc.sci
.........\..\Lab1.syn_hier_info
.........\..\Lab1.tan.qmsg
.........\..\Lab1.tis_db_list.ddb
.........\..\prev_cmp_Lab1.asm.qmsg
.........\..\prev_cmp_Lab1.fit.qmsg
.........\..\prev_cmp_Lab1.map.qmsg
.........\..\prev_cmp_Lab1.tan.qmsg
.........\..\prev_cmp_Lab1_FPGA.qmsg
.........\Lab1.asm.rpt
.........\Lab1.done
.........\Lab1.dpf
.........\Lab1.fit.rpt
.........\Lab1.fit.smsg
.........\Lab1.fit.summary
.........\Lab1.flow.rpt
.........\Lab1.map.rpt
.........\Lab1.map.summary
.........\Lab1.pin
.........\Lab1.pof
.........\Lab1.qsf
.........\Lab1.sof
.........\Lab1.tan.rpt
.........\Lab1.tan.summary
.........\Lab1.v
.........\Lab1_FPGA.qpf
.........\Lab1_FPGA.qws
.........\Trex_C1_Pin_Table.pdf
.........\db
.........\..\Lab1.asm.qmsg
.........\..\Lab1.cbx.xml
.........\..\Lab1.cmp.bpm
.........\..\Lab1.cmp.cdb
.........\..\Lab1.cmp.ecobp
.........\..\Lab1.cmp.hdb
.........\..\Lab1.cmp.logdb
.........\..\Lab1.cmp.rdb
.........\..\Lab1.cmp.tdb
.........\..\Lab1.cmp0.ddb
.........\..\Lab1.cmp_bb.cdb
.........\..\Lab1.cmp_bb.hdb
.........\..\Lab1.cmp_bb.logdb
.........\..\Lab1.cmp_bb.rcf
.........\..\Lab1.dbp
.........\..\Lab1.db_info
.........\..\Lab1.eco.cdb
.........\..\Lab1.fit.qmsg
.........\..\Lab1.hier_info
.........\..\Lab1.hif
.........\..\Lab1.map.bpm
.........\..\Lab1.map.cdb
.........\..\Lab1.map.ecobp
.........\..\Lab1.map.hdb
.........\..\Lab1.map.logdb
.........\..\Lab1.map.qmsg
.........\..\Lab1.map_bb.cdb
.........\..\Lab1.map_bb.hdb
.........\..\Lab1.map_bb.logdb
.........\..\Lab1.pre_map.cdb
.........\..\Lab1.pre_map.hdb
.........\..\Lab1.psp
.........\..\Lab1.pss
.........\..\Lab1.rtlv.hdb
.........\..\Lab1.rtlv_sg.cdb
.........\..\Lab1.rtlv_sg_swap.cdb
.........\..\Lab1.sgdiff.cdb
.........\..\Lab1.sgdiff.hdb
.........\..\Lab1.signalprobe.cdb
.........\..\Lab1.sld_design_entry.sci
.........\..\Lab1.sld_design_entry_dsc.sci
.........\..\Lab1.syn_hier_info
.........\..\Lab1.tan.qmsg
.........\..\Lab1.tis_db_list.ddb
.........\..\prev_cmp_Lab1.asm.qmsg
.........\..\prev_cmp_Lab1.fit.qmsg
.........\..\prev_cmp_Lab1.map.qmsg
.........\..\prev_cmp_Lab1.tan.qmsg
.........\..\prev_cmp_Lab1_FPGA.qmsg
.........\Lab1.asm.rpt
.........\Lab1.done
.........\Lab1.dpf
.........\Lab1.fit.rpt
.........\Lab1.fit.smsg
.........\Lab1.fit.summary
.........\Lab1.flow.rpt
.........\Lab1.map.rpt
.........\Lab1.map.summary
.........\Lab1.pin
.........\Lab1.pof
.........\Lab1.qsf
.........\Lab1.sof
.........\Lab1.tan.rpt
.........\Lab1.tan.summary
.........\Lab1.v
.........\Lab1_FPGA.qpf
.........\Lab1_FPGA.qws
.........\Trex_C1_Pin_Table.pdf