文件名称:uart
介绍说明－－下载内容均来自于网络，请自行研究使用
Uart port
是一段不错的，完全可综合的verilog源码-Uart port is a good, fully integrated Verilog source code
是一段不错的，完全可综合的verilog源码-Uart port is a good, fully integrated Verilog source code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
uart
....\db
....\..\uart_clk.asm.qmsg
....\..\uart_clk.cbx.xml
....\..\uart_clk.cmp.cdb
....\..\uart_clk.cmp.hdb
....\..\uart_clk.cmp.qrpt
....\..\uart_clk.cmp.rdb
....\..\uart_clk.cmp.tdb
....\..\uart_clk.cmp0.ddb
....\..\uart_clk.dbp
....\..\uart_clk.db_info
....\..\uart_clk.eco.cdb
....\..\uart_clk.eds_overflow
....\..\uart_clk.fit.qmsg
....\..\uart_clk.hier_info
....\..\uart_clk.hif
....\..\uart_clk.map.cdb
....\..\uart_clk.map.hdb
....\..\uart_clk.map.qmsg
....\..\uart_clk.pre_map.cdb
....\..\uart_clk.pre_map.hdb
....\..\uart_clk.psp
....\..\uart_clk.rtlv.hdb
....\..\uart_clk.rtlv_sg.cdb
....\..\uart_clk.rtlv_sg_swap.cdb
....\..\uart_clk.sgdiff.cdb
....\..\uart_clk.sgdiff.hdb
....\..\uart_clk.signalprobe.cdb
....\..\uart_clk.sim.hdb
....\..\uart_clk.sim.qmsg
....\..\uart_clk.sim.qrpt
....\..\uart_clk.sim.rdb
....\..\uart_clk.sim.vwf
....\..\uart_clk.sld_design_entry.sci
....\..\uart_clk.sld_design_entry_dsc.sci
....\..\uart_clk.syn_hier_info
....\..\uart_clk.tan.qmsg
....\..\uart_emitter.asm.qmsg
....\..\uart_emitter.cbx.xml
....\..\uart_emitter.cmp.cdb
....\..\uart_emitter.cmp.hdb
....\..\uart_emitter.cmp.qrpt
....\..\uart_emitter.cmp.rdb
....\..\uart_emitter.cmp.tdb
....\..\uart_emitter.cmp0.ddb
....\..\uart_emitter.dbp
....\..\uart_emitter.db_info
....\..\uart_emitter.eco.cdb
....\..\uart_emitter.eds_overflow
....\..\uart_emitter.fit.qmsg
....\..\uart_emitter.hier_info
....\..\uart_emitter.hif
....\..\uart_emitter.map.cdb
....\..\uart_emitter.map.hdb
....\..\uart_emitter.map.qmsg
....\..\uart_emitter.pre_map.cdb
....\..\uart_emitter.pre_map.hdb
....\..\uart_emitter.psp
....\..\uart_emitter.rtlv.hdb
....\..\uart_emitter.rtlv_sg.cdb
....\..\uart_emitter.rtlv_sg_swap.cdb
....\..\uart_emitter.sgdiff.cdb
....\..\uart_emitter.sgdiff.hdb
....\..\uart_emitter.signalprobe.cdb
....\..\uart_emitter.sim.hdb
....\..\uart_emitter.sim.qmsg
....\..\uart_emitter.sim.qrpt
....\..\uart_emitter.sim.rdb
....\..\uart_emitter.sim.vwf
....\..\uart_emitter.sld_design_entry.sci
....\..\uart_emitter.sld_design_entry_dsc.sci
....\..\uart_emitter.smp_dump.txt
....\..\uart_emitter.syn_hier_info
....\..\uart_emitter.tan.qmsg
....\..\uart_receive.asm.qmsg
....\..\uart_receive.cbx.xml
....\..\uart_receive.cmp.cdb
....\..\uart_receive.cmp.hdb
....\..\uart_receive.cmp.qrpt
....\..\uart_receive.cmp.rdb
....\..\uart_receive.cmp.tdb
....\..\uart_receive.cmp0.ddb
....\..\uart_receive.dbp
....\..\uart_receive.db_info
....\..\uart_receive.eco.cdb
....\..\uart_receive.eds_overflow
....\..\uart_receive.fit.qmsg
....\..\uart_receive.hier_info
....\..\uart_receive.hif
....\..\uart_receive.map.cdb
....\..\uart_receive.map.hdb
....\..\uart_receive.map.qmsg
....\..\uart_receive.pre_map.cdb
....\..\uart_receive.pre_map.hdb
....\..\uart_receive.psp
....\..\uart_receive.rtlv.hdb
....\..\uart_receive.rtlv_sg.cdb
....\..\uart_receive.rtlv_sg_swap.cdb
....\..\uart_receive.sgdiff.cdb
....\db
....\..\uart_clk.asm.qmsg
....\..\uart_clk.cbx.xml
....\..\uart_clk.cmp.cdb
....\..\uart_clk.cmp.hdb
....\..\uart_clk.cmp.qrpt
....\..\uart_clk.cmp.rdb
....\..\uart_clk.cmp.tdb
....\..\uart_clk.cmp0.ddb
....\..\uart_clk.dbp
....\..\uart_clk.db_info
....\..\uart_clk.eco.cdb
....\..\uart_clk.eds_overflow
....\..\uart_clk.fit.qmsg
....\..\uart_clk.hier_info
....\..\uart_clk.hif
....\..\uart_clk.map.cdb
....\..\uart_clk.map.hdb
....\..\uart_clk.map.qmsg
....\..\uart_clk.pre_map.cdb
....\..\uart_clk.pre_map.hdb
....\..\uart_clk.psp
....\..\uart_clk.rtlv.hdb
....\..\uart_clk.rtlv_sg.cdb
....\..\uart_clk.rtlv_sg_swap.cdb
....\..\uart_clk.sgdiff.cdb
....\..\uart_clk.sgdiff.hdb
....\..\uart_clk.signalprobe.cdb
....\..\uart_clk.sim.hdb
....\..\uart_clk.sim.qmsg
....\..\uart_clk.sim.qrpt
....\..\uart_clk.sim.rdb
....\..\uart_clk.sim.vwf
....\..\uart_clk.sld_design_entry.sci
....\..\uart_clk.sld_design_entry_dsc.sci
....\..\uart_clk.syn_hier_info
....\..\uart_clk.tan.qmsg
....\..\uart_emitter.asm.qmsg
....\..\uart_emitter.cbx.xml
....\..\uart_emitter.cmp.cdb
....\..\uart_emitter.cmp.hdb
....\..\uart_emitter.cmp.qrpt
....\..\uart_emitter.cmp.rdb
....\..\uart_emitter.cmp.tdb
....\..\uart_emitter.cmp0.ddb
....\..\uart_emitter.dbp
....\..\uart_emitter.db_info
....\..\uart_emitter.eco.cdb
....\..\uart_emitter.eds_overflow
....\..\uart_emitter.fit.qmsg
....\..\uart_emitter.hier_info
....\..\uart_emitter.hif
....\..\uart_emitter.map.cdb
....\..\uart_emitter.map.hdb
....\..\uart_emitter.map.qmsg
....\..\uart_emitter.pre_map.cdb
....\..\uart_emitter.pre_map.hdb
....\..\uart_emitter.psp
....\..\uart_emitter.rtlv.hdb
....\..\uart_emitter.rtlv_sg.cdb
....\..\uart_emitter.rtlv_sg_swap.cdb
....\..\uart_emitter.sgdiff.cdb
....\..\uart_emitter.sgdiff.hdb
....\..\uart_emitter.signalprobe.cdb
....\..\uart_emitter.sim.hdb
....\..\uart_emitter.sim.qmsg
....\..\uart_emitter.sim.qrpt
....\..\uart_emitter.sim.rdb
....\..\uart_emitter.sim.vwf
....\..\uart_emitter.sld_design_entry.sci
....\..\uart_emitter.sld_design_entry_dsc.sci
....\..\uart_emitter.smp_dump.txt
....\..\uart_emitter.syn_hier_info
....\..\uart_emitter.tan.qmsg
....\..\uart_receive.asm.qmsg
....\..\uart_receive.cbx.xml
....\..\uart_receive.cmp.cdb
....\..\uart_receive.cmp.hdb
....\..\uart_receive.cmp.qrpt
....\..\uart_receive.cmp.rdb
....\..\uart_receive.cmp.tdb
....\..\uart_receive.cmp0.ddb
....\..\uart_receive.dbp
....\..\uart_receive.db_info
....\..\uart_receive.eco.cdb
....\..\uart_receive.eds_overflow
....\..\uart_receive.fit.qmsg
....\..\uart_receive.hier_info
....\..\uart_receive.hif
....\..\uart_receive.map.cdb
....\..\uart_receive.map.hdb
....\..\uart_receive.map.qmsg
....\..\uart_receive.pre_map.cdb
....\..\uart_receive.pre_map.hdb
....\..\uart_receive.psp
....\..\uart_receive.rtlv.hdb
....\..\uart_receive.rtlv_sg.cdb
....\..\uart_receive.rtlv_sg_swap.cdb
....\..\uart_receive.sgdiff.cdb