文件名称:yibuqinglin
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含异步清0和同步时钟使能的4位加法计数器
含计数使能,异步复位和计数值并行预置功能4位加法计数器,由实验图1所示,图中间是4位锁存器 rst是异步清信号,高电平有效 clk是锁存信号 D[3..0]是4位数据输入端.当ENA为 1 时,多路选择器将加1器的输出值加载于锁存器的数据端 当ENA为 0 时将"0000"加载于锁存器.-With asynchronous and synchronous clock clearance 0 enabled four adder counter with count enable, asynchronous reset and preset functions of numerical parallel adder four counters, by the experiment shown in Figure 1, Figure 4 middle latch rst is asynchronous clearance signal, high effective signal clk is Latched D [3 .. 0] is 4-bit data input. When ENA for 1:00, MUX will increase the output value of 1 load in latch data terminal when the ENA for the 0:00 to 0000 add-in latch.
含计数使能,异步复位和计数值并行预置功能4位加法计数器,由实验图1所示,图中间是4位锁存器 rst是异步清信号,高电平有效 clk是锁存信号 D[3..0]是4位数据输入端.当ENA为 1 时,多路选择器将加1器的输出值加载于锁存器的数据端 当ENA为 0 时将"0000"加载于锁存器.-With asynchronous and synchronous clock clearance 0 enabled four adder counter with count enable, asynchronous reset and preset functions of numerical parallel adder four counters, by the experiment shown in Figure 1, Figure 4 middle latch rst is asynchronous clearance signal, high effective signal clk is Latched D [3 .. 0] is 4-bit data input. When ENA for 1:00, MUX will increase the output value of 1 load in latch data terminal when the ENA for the 0:00 to 0000 add-in latch.
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