文件名称:S7_UART

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.48mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • z**
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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S7_UART串口输出,运行在quartus50中-S7_UART serial output, running on quartus50 in
相关搜索: S7_UART
uart
vh

(系统自动生成,下载前可以参看下载内容)

下载文件列表

S7_UART

.......\Doc

.......\...\sscom.ini

.......\...\sscom32.exe

.......\...\UART控制器设计说明.doc

.......\...\xapp341.pdf

.......\func_sim

.......\........\rcvr.v

.......\........\transcript

.......\........\txmit.v

.......\........\txmit_tf.do

.......\........\uart.cr.mti

.......\........\uart.mpf

.......\........\uart.v

.......\........\uart_if.v

.......\........\uart_tb.do

.......\........\uart_tb.v

.......\........\uart_tb_fixed.do

.......\........\vish_stacktrace.vstf

.......\........\vsim.wlf

.......\........\wave.do

.......\........\work

.......\........\....\@u@a@r@t_tb

.......\........\....\...........\verilog.asm

.......\........\....\...........\_primary.dat

.......\........\....\...........\_primary.vhd

.......\........\....\rcvr

.......\........\....\....\verilog.asm

.......\........\....\....\_primary.dat

.......\........\....\....\_primary.vhd

.......\........\....\txmit

.......\........\....\.....\verilog.asm

.......\........\....\.....\_primary.dat

.......\........\....\.....\_primary.vhd

.......\........\....\uart

.......\........\....\....\verilog.asm

.......\........\....\....\_primary.dat

.......\........\....\....\_primary.vhd

.......\........\....\uart_if

.......\........\....\.......\verilog.asm

.......\........\....\.......\_primary.dat

.......\........\....\.......\_primary.vhd

.......\........\....\_info

.......\physical

.......\........\altclklock0.bsf

.......\........\altclklock0.v

.......\........\altclklock0_bb.v

.......\........\async_transmitter.bsf

.......\........\cmp_state.ini

.......\........\db

.......\........\..\altsyncram_2dq.tdf

.......\........\..\altsyncram_8tj.tdf

.......\........\..\altsyncram_9un.tdf

.......\........\..\altsyncram_g5q.tdf

.......\........\..\cntr_cs6.tdf

.......\........\..\cntr_gs6.tdf

.......\........\..\cntr_ub7.tdf

.......\........\..\cntr_vt6.tdf

.......\........\..\uart_if.asm.qmsg

.......\........\..\uart_if.asm_labs.ddb

.......\........\..\uart_if.cbx.xml

.......\........\..\uart_if.cmp.cdb

.......\........\..\uart_if.cmp.hdb

.......\........\..\uart_if.cmp.logdb

.......\........\..\uart_if.cmp.rdb

.......\........\..\uart_if.cmp.tdb

.......\........\..\uart_if.cmp0.ddb

.......\........\..\uart_if.cmp2.ddb

.......\........\..\uart_if.db_info

.......\........\..\uart_if.eco.cdb

.......\........\..\uart_if.eda.qmsg

.......\........\..\uart_if.fit.qmsg

.......\........\..\uart_if.hier_info

.......\........\..\uart_if.hif

.......\........\..\uart_if.map.cdb

.......\........\..\uart_if.map.hdb

.......\........\..\uart_if.map.logdb

.......\........\..\uart_if.map.qmsg

.......\........\..\uart_if.pre_map.cdb

.......\........\..\uart_if.pre_map.hdb

.......\........\..\uart_if.psp

.......\........\..\uart_if.rtlv.hdb

.......\........\..\uart_if.rtlv_sg.cdb

.......\........\..\uart_if.rtlv_sg_swap.cdb

.......\........\..\uart_if.sgdiff.cdb

.......\........\..\uart_if.sgdiff.hdb

.......\........\..\uart_if.signalprobe.cdb

.......\........\..\uart_if.sld_design_entry.sci

.......\........\..\uart_if.sld_design_entry_dsc.sci

.......\........\..\uart_if.syn_hier_info

.......\........\..\uart_if.tan.qmsg

.......\........\..\uart_if_cmp.qrpt

.......\........\..\uart_if_hier_info

.......\........\..\uart_if_syn_hier_info

.......\........\div.bsf

.......\........\div_2.bsf

.......\........\div_2.v

.......\........\filter.bsf

.......\........\LED_flush.bsf

.......\........\rcvr.bsf

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