文件名称:usb_funct
介绍说明－－下载内容均来自于网络，请自行研究使用
usb2.0 ip 文挡齐全,并已经过FPGA的验证,希望大家支持-usb2.0 ip complete text block, and has been FPGA verification, I hope you will support
(系统自动生成,下载前可以参看下载内容)
下载文件列表
usb_funct
.........\bench
.........\.....\CVS
.........\.....\...\Entries
.........\.....\...\Repository
.........\.....\...\Root
.........\.....\verilog
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\doc
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\README.txt
.........\...\STATUS.txt
.........\...\usb_doc.pdf
.........\rtl
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\verilog
.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\usbf_crc16.v
.........\...\.......\usbf_crc5.v
.........\...\.......\usbf_defines.v
.........\...\.......\usbf_ep_rf.v
.........\...\.......\usbf_ep_rf_dummy.v
.........\...\.......\usbf_idma.v
.........\...\.......\usbf_mem_arb.v
.........\...\.......\usbf_pa.v
.........\...\.......\usbf_pd.v
.........\...\.......\usbf_pe.v
.........\...\.......\usbf_pl.v
.........\...\.......\usbf_rf.v
.........\...\.......\usbf_top.v
.........\...\.......\usbf_utmi_if.v
.........\...\.......\usbf_utmi_ls.v
.........\...\.......\usbf_wb.v
.........\sim
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\rtl_sim
.........\...\.......\bin
.........\...\.......\...\CVS
.........\...\.......\...\...\Entries
.........\...\.......\...\...\Repository
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.........\...\.......\CVS
.........\...\.......\...\Entries
.........\...\.......\...\Repository
.........\...\.......\...\Root
.........\...\.......\run
.........\...\.......\...\CVS
.........\...\.......\...\...\Entries
.........\...\.......\...\...\Repository
.........\...\.......\...\...\Root
.........\syn
.........\...\bin
.........\...\...\comp.dc
.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
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.........\...\...\design_spec.dc
.........\...\...\lib_spec.dc
.........\...\...\read.dc
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.........\bench
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.........\.....\...\Root
.........\.....\verilog
.........\.....\.......\CVS
.........\.....\.......\...\Entries
.........\.....\.......\...\Repository
.........\.....\.......\...\Root
.........\doc
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.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\README.txt
.........\...\STATUS.txt
.........\...\usb_doc.pdf
.........\rtl
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.........\...\...\Entries
.........\...\...\Repository
.........\...\...\Root
.........\...\verilog
.........\...\.......\CVS
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.........\...\.......\usbf_crc16.v
.........\...\.......\usbf_crc5.v
.........\...\.......\usbf_defines.v
.........\...\.......\usbf_ep_rf.v
.........\...\.......\usbf_ep_rf_dummy.v
.........\...\.......\usbf_idma.v
.........\...\.......\usbf_mem_arb.v
.........\...\.......\usbf_pa.v
.........\...\.......\usbf_pd.v
.........\...\.......\usbf_pe.v
.........\...\.......\usbf_pl.v
.........\...\.......\usbf_rf.v
.........\...\.......\usbf_top.v
.........\...\.......\usbf_utmi_if.v
.........\...\.......\usbf_utmi_ls.v
.........\...\.......\usbf_wb.v
.........\sim
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.........\syn
.........\...\bin
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.........\...\...\CVS
.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\...\design_spec.dc
.........\...\...\lib_spec.dc
.........\...\...\read.dc
.........\...\CVS
.........\...\...\Entries
.........\...\...\Repository
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.........\...\log
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.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\out
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.........\...\...\...\Entries
.........\...\...\...\Repository
.........\...\...\...\Root
.........\...\run
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.........\...\...\...\Entries
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.........\...\...\...\Root