文件名称:MyThirdProject
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含异步清0和同步时钟使能的加法计数器的设计-With asynchronous and synchronous clock clearance 0 to enable the design of the adder counter
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下载文件列表
MyThirdProject
..............\db
..............\..\add_sub_3rh.tdf
..............\..\add_sub_4rh.tdf
..............\..\add_sub_5rh.tdf
..............\..\add_sub_lsh.tdf
..............\..\add_sub_osh.tdf
..............\..\altsyncram_7ji2.tdf
..............\..\cmpr_fnh.tdf
..............\..\cntr_5af.tdf
..............\..\cntr_dkf.tdf
..............\..\cntr_ebg.tdf
..............\..\cntr_fgh.tdf
..............\..\cntr_nfe.tdf
..............\..\decode_ogi.tdf
..............\..\Dip_PB_Led.asm.qmsg
..............\..\Dip_PB_Led.cbx.xml
..............\..\Dip_PB_Led.cmp.cdb
..............\..\Dip_PB_Led.cmp.hdb
..............\..\Dip_PB_Led.cmp.kpt
..............\..\Dip_PB_Led.cmp.logdb
..............\..\Dip_PB_Led.cmp.rdb
..............\..\Dip_PB_Led.cmp.tdb
..............\..\Dip_PB_Led.cmp0.ddb
..............\..\Dip_PB_Led.dbp
..............\..\Dip_PB_Led.db_info
..............\..\Dip_PB_Led.eco.cdb
..............\..\Dip_PB_Led.eds_overflow
..............\..\Dip_PB_Led.fit.qmsg
..............\..\Dip_PB_Led.fnsim.cdb
..............\..\Dip_PB_Led.fnsim.hdb
..............\..\Dip_PB_Led.fnsim.qmsg
..............\..\Dip_PB_Led.hier_info
..............\..\Dip_PB_Led.hif
..............\..\Dip_PB_Led.map.cdb
..............\..\Dip_PB_Led.map.hdb
..............\..\Dip_PB_Led.map.logdb
..............\..\Dip_PB_Led.map.qmsg
..............\..\Dip_PB_Led.pre_map.cdb
..............\..\Dip_PB_Led.pre_map.hdb
..............\..\Dip_PB_Led.psp
..............\..\Dip_PB_Led.rpp.qmsg
..............\..\Dip_PB_Led.rtlv.hdb
..............\..\Dip_PB_Led.rtlv_sg.cdb
..............\..\Dip_PB_Led.rtlv_sg_swap.cdb
..............\..\Dip_PB_Led.sgate.rvd
..............\..\Dip_PB_Led.sgate_sm.rvd
..............\..\Dip_PB_Led.sgdiff.cdb
..............\..\Dip_PB_Led.sgdiff.hdb
..............\..\Dip_PB_Led.signalprobe.cdb
..............\..\Dip_PB_Led.sim.hdb
..............\..\Dip_PB_Led.sim.qmsg
..............\..\Dip_PB_Led.sim.rdb
..............\..\Dip_PB_Led.sim.vwf
..............\..\Dip_PB_Led.sim_ori.vwf
..............\..\Dip_PB_Led.sld_design_entry.sci
..............\..\Dip_PB_Led.sld_design_entry_dsc.sci
..............\..\Dip_PB_Led.syn_hier_info
..............\..\Dip_PB_Led.tan.qmsg
..............\..\mux_3ec.tdf
..............\..\wed.zsf
..............\Dip_PB_Led.asm.rpt
..............\Dip_PB_Led.cdf
..............\Dip_PB_Led.done
..............\Dip_PB_Led.dpf
..............\Dip_PB_Led.fit.rpt
..............\Dip_PB_Led.fit.smsg
..............\Dip_PB_Led.fit.summary
..............\Dip_PB_Led.flow.rpt
..............\Dip_PB_Led.map.rpt
..............\Dip_PB_Led.map.summary
..............\Dip_PB_Led.pin
..............\Dip_PB_Led.pof
..............\Dip_PB_Led.qpf
..............\Dip_PB_Led.qsf
..............\Dip_PB_Led.qws
..............\Dip_PB_Led.sim.rpt
..............\Dip_PB_Led.sof
..............\Dip_PB_Led.tan.rpt
..............\Dip_PB_Led.tan.summary
..............\Dip_PB_Led.vhd
..............\Dip_PB_Led.vwf
..............\stp1.stp
..............\db
..............\..\add_sub_3rh.tdf
..............\..\add_sub_4rh.tdf
..............\..\add_sub_5rh.tdf
..............\..\add_sub_lsh.tdf
..............\..\add_sub_osh.tdf
..............\..\altsyncram_7ji2.tdf
..............\..\cmpr_fnh.tdf
..............\..\cntr_5af.tdf
..............\..\cntr_dkf.tdf
..............\..\cntr_ebg.tdf
..............\..\cntr_fgh.tdf
..............\..\cntr_nfe.tdf
..............\..\decode_ogi.tdf
..............\..\Dip_PB_Led.asm.qmsg
..............\..\Dip_PB_Led.cbx.xml
..............\..\Dip_PB_Led.cmp.cdb
..............\..\Dip_PB_Led.cmp.hdb
..............\..\Dip_PB_Led.cmp.kpt
..............\..\Dip_PB_Led.cmp.logdb
..............\..\Dip_PB_Led.cmp.rdb
..............\..\Dip_PB_Led.cmp.tdb
..............\..\Dip_PB_Led.cmp0.ddb
..............\..\Dip_PB_Led.dbp
..............\..\Dip_PB_Led.db_info
..............\..\Dip_PB_Led.eco.cdb
..............\..\Dip_PB_Led.eds_overflow
..............\..\Dip_PB_Led.fit.qmsg
..............\..\Dip_PB_Led.fnsim.cdb
..............\..\Dip_PB_Led.fnsim.hdb
..............\..\Dip_PB_Led.fnsim.qmsg
..............\..\Dip_PB_Led.hier_info
..............\..\Dip_PB_Led.hif
..............\..\Dip_PB_Led.map.cdb
..............\..\Dip_PB_Led.map.hdb
..............\..\Dip_PB_Led.map.logdb
..............\..\Dip_PB_Led.map.qmsg
..............\..\Dip_PB_Led.pre_map.cdb
..............\..\Dip_PB_Led.pre_map.hdb
..............\..\Dip_PB_Led.psp
..............\..\Dip_PB_Led.rpp.qmsg
..............\..\Dip_PB_Led.rtlv.hdb
..............\..\Dip_PB_Led.rtlv_sg.cdb
..............\..\Dip_PB_Led.rtlv_sg_swap.cdb
..............\..\Dip_PB_Led.sgate.rvd
..............\..\Dip_PB_Led.sgate_sm.rvd
..............\..\Dip_PB_Led.sgdiff.cdb
..............\..\Dip_PB_Led.sgdiff.hdb
..............\..\Dip_PB_Led.signalprobe.cdb
..............\..\Dip_PB_Led.sim.hdb
..............\..\Dip_PB_Led.sim.qmsg
..............\..\Dip_PB_Led.sim.rdb
..............\..\Dip_PB_Led.sim.vwf
..............\..\Dip_PB_Led.sim_ori.vwf
..............\..\Dip_PB_Led.sld_design_entry.sci
..............\..\Dip_PB_Led.sld_design_entry_dsc.sci
..............\..\Dip_PB_Led.syn_hier_info
..............\..\Dip_PB_Led.tan.qmsg
..............\..\mux_3ec.tdf
..............\..\wed.zsf
..............\Dip_PB_Led.asm.rpt
..............\Dip_PB_Led.cdf
..............\Dip_PB_Led.done
..............\Dip_PB_Led.dpf
..............\Dip_PB_Led.fit.rpt
..............\Dip_PB_Led.fit.smsg
..............\Dip_PB_Led.fit.summary
..............\Dip_PB_Led.flow.rpt
..............\Dip_PB_Led.map.rpt
..............\Dip_PB_Led.map.summary
..............\Dip_PB_Led.pin
..............\Dip_PB_Led.pof
..............\Dip_PB_Led.qpf
..............\Dip_PB_Led.qsf
..............\Dip_PB_Led.qws
..............\Dip_PB_Led.sim.rpt
..............\Dip_PB_Led.sof
..............\Dip_PB_Led.tan.rpt
..............\Dip_PB_Led.tan.summary
..............\Dip_PB_Led.vhd
..............\Dip_PB_Led.vwf
..............\stp1.stp