文件名称:EHERNETIPcore
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该文件包含以太网IP核的相关代码，一共包含24个VERILOG源代码-This document contains the relevant Ethernet IP core code, a total of 24 includes Verilog source code
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下载文件列表
以太网IP core
.............\eth_clockgen.v
.............\eth_crc.v
.............\eth_defines.v
.............\eth_maccontrol.v
.............\eth_macstatus.v
.............\eth_miim.v
.............\eth_outputcontrol.v
.............\eth_random.v
.............\eth_receivecontrol.v
.............\eth_register.v
.............\eth_registers.v
.............\eth_rxcounters.v
.............\eth_rxethmac.v
.............\eth_rxstatem.v
.............\eth_shiftreg.v
.............\eth_sync_clk1_clk2.v
.............\eth_top.v
.............\eth_transmitcontrol.v
.............\eth_txcounters.v
.............\eth_txethmac.v
.............\eth_txstatem.v
.............\eth_wishbonedma.v
.............\tb_eth_top.v
.............\timescale.v
.............\eth_clockgen.v
.............\eth_crc.v
.............\eth_defines.v
.............\eth_maccontrol.v
.............\eth_macstatus.v
.............\eth_miim.v
.............\eth_outputcontrol.v
.............\eth_random.v
.............\eth_receivecontrol.v
.............\eth_register.v
.............\eth_registers.v
.............\eth_rxcounters.v
.............\eth_rxethmac.v
.............\eth_rxstatem.v
.............\eth_shiftreg.v
.............\eth_sync_clk1_clk2.v
.............\eth_top.v
.............\eth_transmitcontrol.v
.............\eth_txcounters.v
.............\eth_txethmac.v
.............\eth_txstatem.v
.............\eth_wishbonedma.v
.............\tb_eth_top.v
.............\timescale.v