文件名称:reg_counter
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程序补充说明：时钟输入：在每个时钟的正沿或负沿对数据进行处理。时钟的正沿有效还是负沿有效，是由always敏感表中的posedge或negedge决定的 -Procedures for additional information: Clock Input: in each clock is along or negative along the data treatment. Clock is along the effective or negative along the effective, is always sensitive table posedge or negedge decision
相关搜索： counter
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Example-4-4
...........\reg_counter.prd
...........\reg_counter.prj
...........\reg_counter.v
...........\rev_2
...........\.....\par_1
...........\.....\reg_counter.edf
...........\.....\reg_counter.fse
...........\.....\reg_counter.ncf
...........\.....\reg_counter.srd
...........\.....\reg_counter.srm
...........\.....\reg_counter.srr
...........\.....\reg_counter.srs
...........\.....\reg_counter.tlg
...........\.....\rpt_reg_counter.areasrr
...........\.....\rpt_reg_counter_areasrr.htm
...........\.....\syntmp
...........\.....\......\reg_counter.msg
...........\.....\......\reg_counter.plg
...........\.....\verif
...........\.....\.....\reg_counter.vif
...........\sim
...........\...\reg_counter.v
...........\source
...........\......\reg_counter.v
...........\示例说明.doc
...........\reg_counter.prd
...........\reg_counter.prj
...........\reg_counter.v
...........\rev_2
...........\.....\par_1
...........\.....\reg_counter.edf
...........\.....\reg_counter.fse
...........\.....\reg_counter.ncf
...........\.....\reg_counter.srd
...........\.....\reg_counter.srm
...........\.....\reg_counter.srr
...........\.....\reg_counter.srs
...........\.....\reg_counter.tlg
...........\.....\rpt_reg_counter.areasrr
...........\.....\rpt_reg_counter_areasrr.htm
...........\.....\syntmp
...........\.....\......\reg_counter.msg
...........\.....\......\reg_counter.plg
...........\.....\verif
...........\.....\.....\reg_counter.vif
...........\sim
...........\...\reg_counter.v
...........\source
...........\......\reg_counter.v
...........\示例说明.doc