VHDL具有设计重用、大型设计能力、可读性强、易于编译等优点逐渐受到硬件设计者的青睐。但是，VHDL是一门语法相当严格的语言，易学性差，特别是对于刚开始接触VHDL的设计者而言，经常会因某些小细节处理不当导致综合无法通过。为此本文就其中一些比较典型的问题展开探讨，-Design Reuse with VHDL, the designed capacity of large-scale, readable, and easy to compile the advantages of increasing the hardware designers of all ages. However, VHDL is a very strict grammar of the language, to learn poor, especially for the beginning of the designers of VHDL in terms of contacts, often due to improper handling of some small details can not lead to comprehensive. To this end this article on some of the more typical issues discussed