文件名称:Xil3SD1800A_MIG_ISIM_vlog_v92
- 所属分类：
- VHDL编程
- 资源属性：
- [Excel]
- 上传时间：
- 2012-11-26
- 文件大小：
- 3.23mb
- 下载次数：
- 0次
- 提 供 者：
- king52310*********
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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Xilinx DDR2存储器接口调试代码，主频167Mhz，嵌入了CHIPSCORP代码。-Xilinx DDR2 memory interface debug code, frequency 167Mhz, embedded code CHIPSCORP.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Xil3SD1800A_MIG_ISIM_vlog_v92
.............................\ddr2_32Mx32_vlog
.............................\................\ddr2_32Mx32
.............................\................\...........\docs
.............................\................\...........\....\adr_cntrl_timing_0.xls
.............................\................\...........\....\read_data_timing_0.xls
.............................\................\...........\....\write_data_timing_0.xls
.............................\................\...........\example_design
.............................\................\...........\..............\datasheet.txt
.............................\................\...........\..............\log.txt
.............................\................\...........\..............\mig.prj
.............................\................\...........\..............\par
.............................\................\...........\..............\...\automake.log
.............................\................\...........\..............\...\create_ise.bat
.............................\................\...........\..............\...\ddr2_32Mx32.ucf
.............................\................\...........\..............\...\ddr2_32Mx32_summary.html
.............................\................\...........\..............\...\ddr2_speedway.bat
.............................\................\...........\..............\...\ddr2_speedway.ise
.............................\................\...........\..............\...\ddr2_speedway.ise_ISE_Backup
.............................\................\...........\..............\...\ddr2_speedway.restore
.............................\................\...........\..............\...\example.xwv
.............................\................\...........\..............\...\ise_flow.bat
.............................\................\...........\..............\...\ise_run.txt
.............................\................\...........\..............\...\isim
.............................\................\...........\..............\...\....\temp
.............................\................\...........\..............\...\....\....\hdllib.ref
.............................\................\...........\..............\...\....\....\hdpdeps.ref
.............................\................\...........\..............\...\....\....\vlg02
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__infrastructure.bin
.............................\................\...........\..............\...\....\....\vlg0D
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__infrastructure__iobs__0.bin
.............................\................\...........\..............\...\....\....\vlg0F
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__dqs__delay.bin
.............................\................\...........\..............\...\....\....\vlg10
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__controller__iobs__0.bin
.............................\................\...........\..............\...\....\....\vlg14
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__controller__0.bin
.............................\................\...........\..............\...\....\....\vlg18
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__addr__gen__0.bin
.............................\................\...........\..............\...\....\....\vlg19
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__fifo__0__wr__en__0.bin
.............................\................\...........\..............\...\....\....\vlg1B
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__cal__ctl.bin
............................
.............................\ddr2_32Mx32_vlog
.............................\................\ddr2_32Mx32
.............................\................\...........\docs
.............................\................\...........\....\adr_cntrl_timing_0.xls
.............................\................\...........\....\read_data_timing_0.xls
.............................\................\...........\....\write_data_timing_0.xls
.............................\................\...........\example_design
.............................\................\...........\..............\datasheet.txt
.............................\................\...........\..............\log.txt
.............................\................\...........\..............\mig.prj
.............................\................\...........\..............\par
.............................\................\...........\..............\...\automake.log
.............................\................\...........\..............\...\create_ise.bat
.............................\................\...........\..............\...\ddr2_32Mx32.ucf
.............................\................\...........\..............\...\ddr2_32Mx32_summary.html
.............................\................\...........\..............\...\ddr2_speedway.bat
.............................\................\...........\..............\...\ddr2_speedway.ise
.............................\................\...........\..............\...\ddr2_speedway.ise_ISE_Backup
.............................\................\...........\..............\...\ddr2_speedway.restore
.............................\................\...........\..............\...\example.xwv
.............................\................\...........\..............\...\ise_flow.bat
.............................\................\...........\..............\...\ise_run.txt
.............................\................\...........\..............\...\isim
.............................\................\...........\..............\...\....\temp
.............................\................\...........\..............\...\....\....\hdllib.ref
.............................\................\...........\..............\...\....\....\hdpdeps.ref
.............................\................\...........\..............\...\....\....\vlg02
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__infrastructure.bin
.............................\................\...........\..............\...\....\....\vlg0D
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__infrastructure__iobs__0.bin
.............................\................\...........\..............\...\....\....\vlg0F
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__dqs__delay.bin
.............................\................\...........\..............\...\....\....\vlg10
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__controller__iobs__0.bin
.............................\................\...........\..............\...\....\....\vlg14
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__controller__0.bin
.............................\................\...........\..............\...\....\....\vlg18
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__addr__gen__0.bin
.............................\................\...........\..............\...\....\....\vlg19
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__fifo__0__wr__en__0.bin
.............................\................\...........\..............\...\....\....\vlg1B
.............................\................\...........\..............\...\....\....\.....\ddr2__32_mx32__cal__ctl.bin
............................