介绍了3DES加密算法的原理并详尽描述了该算法的FPGA设计实现。采用了状态机和流水线技术，使得在面积和速度上达到最佳优化；添加了输入和输出接口的设计以增强该算法应用的灵活性。各模块均用硬件描述语言实现，最终下载到FPGA芯片Stratix EP1S25F780C5中。-3DES encryption algorithm, introduced the principle and detailed descr iption of the FPGA algorithm design. Use of state machine and pipelining technology, makes the size and speed to achieve the best optimization　added input and output interface design to enhance the flexibility of the application of the algorithm. Each module are used hardware descr iption language to achieve, and ultimately downloaded to the FPGA chip in Stratix EP1S25F780C5.