文件名称:Project_Navigator_Demo

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 107kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 3***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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双向控制全加器的VHDL实现 内含ISE工程文件-Bi-directional control of the full adder VHDL realize intron ISE project file
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下载文件列表

Project_Navigator_Demo

......................\counter

......................\.......\automake.log

......................\.......\bitgen.ut

......................\.......\coregen.log

......................\.......\coregen.prj

......................\.......\counter.bgn

......................\.......\counter.bit

......................\.......\counter.bld

......................\.......\counter.cmd_log

......................\.......\counter.dhp

......................\.......\counter.dly

......................\.......\counter.drc

......................\.......\counter.lso

......................\.......\counter.mrp

......................\.......\counter.nc1

......................\.......\counter.ncd

......................\.......\counter.ngc

......................\.......\counter.ngd

......................\.......\counter.ngm

......................\.......\counter.ngr

......................\.......\counter.npl

......................\.......\counter.pad

......................\.......\counter.pad_txt

......................\.......\counter.par

......................\.......\counter.pcf

......................\.......\counter.placed_ncd_tracker

......................\.......\counter.prj

......................\.......\counter.ptf

......................\.......\counter.routed_ncd_tracker

......................\.......\counter.sprj

......................\.......\counter.stx

......................\.......\counter.syr

......................\.......\counter.tfi

......................\.......\counter.twr

......................\.......\counter.twx

......................\.......\counter.ut

......................\.......\counter.v

......................\.......\counter.xpi

......................\.......\counter_fpga_editor.log

......................\.......\counter_ise5_bak.zip

......................\.......\counter_last_par.ncd

......................\.......\counter_map.ncd

......................\.......\counter_map.ngm

......................\.......\counter_ngdbuild.nav

......................\.......\counter_pad.csv

......................\.......\counter_pad.txt

......................\.......\counter_vhdl.prj

......................\.......\xst

......................\.......\...\work

......................\.......\...\....\hdllib.ref

......................\.......\...\....\vlg10

......................\.......\...\....\.....\counter.bin

......................\.......\_ngo

......................\.......\....\netlist.lst

......................\.......\__projnav

......................\.......\.........\bitgen.rsp

......................\.......\.........\coregen.rsp

......................\.......\.........\counter.gfl

......................\.......\.........\counter.xst

......................\.......\.........\counter._prj

......................\.......\.........\counter._sprj

......................\.......\.........\counter_flowplus.gfl

......................\.......\.........\counter_jhdparse_tcl.rsp

......................\.......\.........\counter_ncdTOut_tcl.rsp

......................\.......\.........\counter_tst_Fix_jhdparse_tcl.rsp

......................\.......\.........\ednTOngd_tcl.rsp

......................\.......\.........\hb_cmds

......................\.......\.........\map.log

......................\.......\.........\nc1TOncd_tcl.rsp

......................\.......\.........\par.log

......................\.......\.........\pfea_tcl.rsp

......................\.......\.........\posttrc.log

......................\.......\.........\runXst_tcl.rsp

......................\.......\__projnav.log

......................\源代码

......................\......\counter.v

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