文件名称:testuart2
- 所属分类：
- 串口编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 348kb
- 下载次数：
- 0次
- 提 供 者：
- yangzh******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog语言，硬件调试，用于actel刚推出的fusion系列芯片的接口调试-Verilog language, the hardware debugger for Actel recently launched series of fusion-chip debug interface
(系统自动生成,下载前可以参看下载内容)
下载文件列表
testuart2
.........\component
.........\constraint
.........\coreconsole
.........\designer
.........\........\impl1
.........\........\.....\designer.log
.........\........\.....\designer_genhdl.log
.........\........\.....\simulation
.........\........\.....\uart_test.adb
.........\........\.....\uart_test.dtf
.........\........\.....\.............\verify.log
.........\........\.....\uart_test.ide_des
.........\........\.....\uart_test.pdb
.........\........\.....\uart_test.pdb.depends
.........\........\.....\uart_test.tcl
.........\........\.....\uart_test_ba.sdf
.........\........\.....\uart_test_ba.v
.........\........\.....\uart_test_fp
.........\........\.....\............\$$FlashPro_FPBBALTLPT1.L$$
.........\........\.....\............\projectData
.........\........\.....\............\...........\uart_test.pdb
.........\........\.....\............\uart_test.log
.........\........\.....\............\uart_test.pro
.........\hdl
.........\...\rec.v
.........\...\send.v
.........\...\uart_test.v
.........\phy_synthesis
.........\simulation
.........\..........\modelsim.ini
.........\smartgen
.........\........\smartgen.aws
.........\stimulus
.........\synthesis
.........\.........\.recordref
.........\.........\backup
.........\.........\run_options.txt
.........\.........\stdout.log
.........\.........\syntmp
.........\.........\......\sap.log
.........\.........\......\uart_test.plg
.........\.........\......\uart_test_flink.htm
.........\.........\......\uart_test_srr.htm
.........\.........\......\uart_test_toc.htm
.........\.........\traplog.tlg
.........\.........\uart_test.areasrr
.........\.........\uart_test.edn
.........\.........\uart_test.fse
.........\.........\uart_test.htm
.........\.........\uart_test.map
.........\.........\uart_test.sap
.........\.........\uart_test.sdf
.........\.........\uart_test.so
.........\.........\uart_test.srd
.........\.........\uart_test.srm
.........\.........\uart_test.srr
.........\.........\uart_test.srs
.........\.........\uart_test.tlg
.........\.........\uart_test_drc.rpt
.........\.........\uart_test_sdc.sdc
.........\.........\uart_test_syn.prj
.........\testuart2.prj
.........\viewdraw
.........\........\sch
.........\........\sym
.........\........\vf
.........\........\..\project.lst
.........\........\viewdraw.ini
.........\........\wir
.........\component
.........\constraint
.........\coreconsole
.........\designer
.........\........\impl1
.........\........\.....\designer.log
.........\........\.....\designer_genhdl.log
.........\........\.....\simulation
.........\........\.....\uart_test.adb
.........\........\.....\uart_test.dtf
.........\........\.....\.............\verify.log
.........\........\.....\uart_test.ide_des
.........\........\.....\uart_test.pdb
.........\........\.....\uart_test.pdb.depends
.........\........\.....\uart_test.tcl
.........\........\.....\uart_test_ba.sdf
.........\........\.....\uart_test_ba.v
.........\........\.....\uart_test_fp
.........\........\.....\............\$$FlashPro_FPBBALTLPT1.L$$
.........\........\.....\............\projectData
.........\........\.....\............\...........\uart_test.pdb
.........\........\.....\............\uart_test.log
.........\........\.....\............\uart_test.pro
.........\hdl
.........\...\rec.v
.........\...\send.v
.........\...\uart_test.v
.........\phy_synthesis
.........\simulation
.........\..........\modelsim.ini
.........\smartgen
.........\........\smartgen.aws
.........\stimulus
.........\synthesis
.........\.........\.recordref
.........\.........\backup
.........\.........\run_options.txt
.........\.........\stdout.log
.........\.........\syntmp
.........\.........\......\sap.log
.........\.........\......\uart_test.plg
.........\.........\......\uart_test_flink.htm
.........\.........\......\uart_test_srr.htm
.........\.........\......\uart_test_toc.htm
.........\.........\traplog.tlg
.........\.........\uart_test.areasrr
.........\.........\uart_test.edn
.........\.........\uart_test.fse
.........\.........\uart_test.htm
.........\.........\uart_test.map
.........\.........\uart_test.sap
.........\.........\uart_test.sdf
.........\.........\uart_test.so
.........\.........\uart_test.srd
.........\.........\uart_test.srm
.........\.........\uart_test.srr
.........\.........\uart_test.srs
.........\.........\uart_test.tlg
.........\.........\uart_test_drc.rpt
.........\.........\uart_test_sdc.sdc
.........\.........\uart_test_syn.prj
.........\testuart2.prj
.........\viewdraw
.........\........\sch
.........\........\sym
.........\........\vf
.........\........\..\project.lst
.........\........\viewdraw.ini
.........\........\wir