文件名称:uart_VHDL
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uart_VHDL
.........\uart 源码 (Verilog)
.........\...................\address_decode.v
.........\...................\clock_divider.v
.........\...................\control_operation.v
.........\...................\cpu_interface.v
.........\...................\serial_interface.v
.........\...................\status_registers.v
.........\...................\tester.v
.........\...................\uart_tb.v
.........\...................\uart_top.v
.........\...................\xmit_rcv_control.v
.........\uart 源码 (Verilog)
.........\...................\address_decode.v
.........\...................\clock_divider.v
.........\...................\control_operation.v
.........\...................\cpu_interface.v
.........\...................\serial_interface.v
.........\...................\status_registers.v
.........\...................\tester.v
.........\...................\uart_tb.v
.........\...................\uart_top.v
.........\...................\xmit_rcv_control.v