文件名称:sc
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用verilog编写的乒乓球游戏，内带ps2，VGA驱动，下载到spantan3开发板上即可使用（原创）-Prepared using Verilog table tennis game, with band ps2, VGA driver, download to spantan3 development board to use (original)
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sc
..\Address_Register.v
..\Alu_RISC.v
..\Alu_RISC_isim_beh.exe
..\Clock_Unit.v
..\Control_Unit.v
..\D_flop.v
..\Instruction_Register.v
..\isim
..\....\work
..\....\....\glbl
..\....\....\....\glbl.h
..\....\....\....\mingw
..\....\....\....\.....\glbl.obj
..\....\....\hdllib.ref
..\....\....\hdpdeps.ref
..\....\....\test___r_i_s_c___s_p_m
..\....\....\......................\mingw
..\....\....\......................\.....\test___r_i_s_c___s_p_m.obj
..\....\....\......................\test___r_i_s_c___s_p_m.h
..\....\....\......................\xsimtest___r_i_s_c___s_p_m.cpp
..\....\....\vlg08
..\....\....\.....\_multiplexer__7ch.bin
..\....\....\vlg0A
..\....\....\.....\_address___register.bin
..\....\....\vlg0C
..\....\....\.....\_register___unit.bin
..\....\....\vlg18
..\....\....\.....\_r_i_s_c___s_p_m.bin
..\....\....\vlg1B
..\....\....\.....\test___r_i_s_c___s_p_m.bin
..\....\....\vlg24
..\....\....\.....\_control___unit.bin
..\....\....\.....\_multiplexer__3ch.bin
..\....\....\vlg2D
..\....\....\.....\glbl.bin
..\....\....\vlg2F
..\....\....\.....\_clock___unit.bin
..\....\....\vlg3A
..\....\....\.....\_instruction___register.bin
..\....\....\vlg44
..\....\....\.....\_processing___unit.bin
..\....\....\vlg4B
..\....\....\.....\_program___counter.bin
..\....\....\vlg4C
..\....\....\.....\_memory___unit.bin
..\....\....\vlg56
..\....\....\.....\_multiplexer__5ch.bin
..\....\....\vlg6E
..\....\....\.....\_alu___r_i_s_c.bin
..\....\....\vlg6F
..\....\....\.....\_multiplexer__6ch.bin
..\....\....\vlg78
..\....\....\.....\_d__flop.bin
..\....\....\_address___register
..\....\....\...................\mingw
..\....\....\...................\.....\_address___register.obj
..\....\....\...................\_address___register.h
..\....\....\_alu___r_i_s_c
..\....\....\..............\mingw
..\....\....\..............\.....\_alu___r_i_s_c.obj
..\....\....\..............\xsim_alu___r_i_s_c.cpp
..\....\....\..............\_alu___r_i_s_c.h
..\....\....\_clock___unit
..\....\....\.............\mingw
..\....\....\.............\.....\_clock___unit.obj
..\....\....\.............\_clock___unit.h
..\....\....\_control___unit
..\....\....\...............\mingw
..\....\....\...............\.....\_control___unit.obj
..\....\....\...............\xsim_control___unit.cpp
..\....\....\...............\_control___unit.h
..\....\....\_d__flop
..\....\....\........\mingw
..\....\....\........\.....\_d__flop.obj
..\....\....\........\_d__flop.h
..\....\....\_instruction___register
..\....\....\.......................\mingw
..\....\....\.......................\.....\_instruction___register.obj
..\....\....\.......................\_instruction___register.h
..\....\....\_memory___unit
..\....\....\..............\mingw
..\....\....\..............\.....\_memory___unit.obj
..\....\....\..............\_memory___unit.h
..\....\....\_multiplexer__3ch
..\....\....\.................\mingw
..\....\....\.................\.....\_multiplexer__3ch.obj
..\....\....\.................\_multiplexer__3ch.h
..\....\....\_multiplexer__5ch
..\....\....\.................\mingw
..\....\....\.................\.....\_multiplexer__5ch.obj
..\....\....\.................\_multiplexer__5ch.h
..\....\....\_multiplexer__6ch
..\....\....\.................\mingw
..\....\....\.................\.....\_multiplexer__6ch.obj
..\....\....\.................\_multiplexer__6ch.h
..\....\....\_multiplexer__7ch
..\....\....\.................\mingw
..\....\....\.................\.....\_multiplexer__7ch.obj
..\....\....\.................\_multiplexer__7ch.h
..\Address_Register.v
..\Alu_RISC.v
..\Alu_RISC_isim_beh.exe
..\Clock_Unit.v
..\Control_Unit.v
..\D_flop.v
..\Instruction_Register.v
..\isim
..\....\work
..\....\....\glbl
..\....\....\....\glbl.h
..\....\....\....\mingw
..\....\....\....\.....\glbl.obj
..\....\....\hdllib.ref
..\....\....\hdpdeps.ref
..\....\....\test___r_i_s_c___s_p_m
..\....\....\......................\mingw
..\....\....\......................\.....\test___r_i_s_c___s_p_m.obj
..\....\....\......................\test___r_i_s_c___s_p_m.h
..\....\....\......................\xsimtest___r_i_s_c___s_p_m.cpp
..\....\....\vlg08
..\....\....\.....\_multiplexer__7ch.bin
..\....\....\vlg0A
..\....\....\.....\_address___register.bin
..\....\....\vlg0C
..\....\....\.....\_register___unit.bin
..\....\....\vlg18
..\....\....\.....\_r_i_s_c___s_p_m.bin
..\....\....\vlg1B
..\....\....\.....\test___r_i_s_c___s_p_m.bin
..\....\....\vlg24
..\....\....\.....\_control___unit.bin
..\....\....\.....\_multiplexer__3ch.bin
..\....\....\vlg2D
..\....\....\.....\glbl.bin
..\....\....\vlg2F
..\....\....\.....\_clock___unit.bin
..\....\....\vlg3A
..\....\....\.....\_instruction___register.bin
..\....\....\vlg44
..\....\....\.....\_processing___unit.bin
..\....\....\vlg4B
..\....\....\.....\_program___counter.bin
..\....\....\vlg4C
..\....\....\.....\_memory___unit.bin
..\....\....\vlg56
..\....\....\.....\_multiplexer__5ch.bin
..\....\....\vlg6E
..\....\....\.....\_alu___r_i_s_c.bin
..\....\....\vlg6F
..\....\....\.....\_multiplexer__6ch.bin
..\....\....\vlg78
..\....\....\.....\_d__flop.bin
..\....\....\_address___register
..\....\....\...................\mingw
..\....\....\...................\.....\_address___register.obj
..\....\....\...................\_address___register.h
..\....\....\_alu___r_i_s_c
..\....\....\..............\mingw
..\....\....\..............\.....\_alu___r_i_s_c.obj
..\....\....\..............\xsim_alu___r_i_s_c.cpp
..\....\....\..............\_alu___r_i_s_c.h
..\....\....\_clock___unit
..\....\....\.............\mingw
..\....\....\.............\.....\_clock___unit.obj
..\....\....\.............\_clock___unit.h
..\....\....\_control___unit
..\....\....\...............\mingw
..\....\....\...............\.....\_control___unit.obj
..\....\....\...............\xsim_control___unit.cpp
..\....\....\...............\_control___unit.h
..\....\....\_d__flop
..\....\....\........\mingw
..\....\....\........\.....\_d__flop.obj
..\....\....\........\_d__flop.h
..\....\....\_instruction___register
..\....\....\.......................\mingw
..\....\....\.......................\.....\_instruction___register.obj
..\....\....\.......................\_instruction___register.h
..\....\....\_memory___unit
..\....\....\..............\mingw
..\....\....\..............\.....\_memory___unit.obj
..\....\....\..............\_memory___unit.h
..\....\....\_multiplexer__3ch
..\....\....\.................\mingw
..\....\....\.................\.....\_multiplexer__3ch.obj
..\....\....\.................\_multiplexer__3ch.h
..\....\....\_multiplexer__5ch
..\....\....\.................\mingw
..\....\....\.................\.....\_multiplexer__5ch.obj
..\....\....\.................\_multiplexer__5ch.h
..\....\....\_multiplexer__6ch
..\....\....\.................\mingw
..\....\....\.................\.....\_multiplexer__6ch.obj
..\....\....\.................\_multiplexer__6ch.h
..\....\....\_multiplexer__7ch
..\....\....\.................\mingw
..\....\....\.................\.....\_multiplexer__7ch.obj
..\....\....\.................\_multiplexer__7ch.h