文件名称:wishbone2avalone
介绍说明－－下载内容均来自于网络，请自行研究使用
由avalen总线转接i2c总线的vhdl程序 可应用于nios嵌入式系统-By avalen bus adapter i2c bus VHDL program can be applied to Nios Embedded Systems
(系统自动生成,下载前可以参看下载内容)
下载文件列表
i2c
...\i2c
...\...\bench
...\...\.....\CVS
...\...\.....\...\Entries
...\...\.....\...\Repository
...\...\.....\...\Root
...\...\.....\verilog
...\...\.....\.......\CVS
...\...\.....\.......\...\Entries
...\...\.....\.......\...\Repository
...\...\.....\.......\...\Root
...\...\.....\.......\i2c_slave_model.v
...\...\.....\.......\spi_slave_model.v
...\...\.....\.......\tst_bench_top.v
...\...\.....\.......\wb_master_model.v
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\doc
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\i2c_specs.pdf
...\...\...\src
...\...\...\...\CVS
...\...\...\...\...\Entries
...\...\...\...\...\Repository
...\...\...\...\...\Root
...\...\documentation
...\...\.............\CVS
...\...\.............\...\Entries
...\...\.............\...\Repository
...\...\.............\...\Root
...\...\rtl
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\verilog
...\...\...\.......\CVS
...\...\...\.......\...\Entries
...\...\...\.......\...\Repository
...\...\...\.......\...\Root
...\...\...\.......\i2c_master_bit_ctrl.v
...\...\...\.......\i2c_master_byte_ctrl.v
...\...\...\.......\i2c_master_defines.v
...\...\...\.......\i2c_master_top.v
...\...\...\.......\timescale.v
...\...\...\vhdl
...\...\...\....\CVS
...\...\...\....\...\Entries
...\...\...\....\...\Repository
...\...\...\....\...\Root
...\...\...\....\I2C.VHD
...\...\...\....\i2c_master_bit_ctrl.vhd
...\...\...\....\i2c_master_byte_ctrl.vhd
...\...\...\....\i2c_master_top.vhd
...\...\...\....\readme
...\...\...\....\tst_ds1621.vhd
...\...\sim
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\i2c_verilog
...\...\...\...........\CVS
...\...\...\...........\...\Entries
...\...\...\...........\...\Repository
...\...\...\...........\...\Root
...\...\...\...........\run
...\...\...\...........\...\bench.vcd
...\...\...\...........\...\CVS
...\...\...\...........\...\...\Entries
...\...\...\...........\...\...\Repository
...\...\...\...........\...\...\Root
...\...\...\...........\...\INCA_libs
...\...\...\...........\...\.........\CVS
...\...\...\...........\...\.........\...\Entries
...\...\...\...........\...\.........\...\Repository
...\...\...\...........\...\.........\...\Root
...\...\...\...........\...\ncverilog.key
...\...\...\...........\...\ncverilog.log
...\...\...\...........\...\run
...\...\...\...........\...\waves
...\...\...\...........\...\.....\CVS
...\...\...\...........\...\.....\...\Entries
...\...\...\...........\...\.....\...\Repository
...\...\...\...........\...\.....\...\Root
...\...\software
...\...\........\CVS
...\...\........\...\Entries
...\...\........\...\Repository
...\...\........\...\Root
...\...\........\drivers
...\...\........\.......\CVS
...\...\........\.......\...\Entries
...\...\........\.......\...\Repository
...\i2c
...\...\bench
...\...\.....\CVS
...\...\.....\...\Entries
...\...\.....\...\Repository
...\...\.....\...\Root
...\...\.....\verilog
...\...\.....\.......\CVS
...\...\.....\.......\...\Entries
...\...\.....\.......\...\Repository
...\...\.....\.......\...\Root
...\...\.....\.......\i2c_slave_model.v
...\...\.....\.......\spi_slave_model.v
...\...\.....\.......\tst_bench_top.v
...\...\.....\.......\wb_master_model.v
...\...\CVS
...\...\...\Entries
...\...\...\Repository
...\...\...\Root
...\...\doc
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\i2c_specs.pdf
...\...\...\src
...\...\...\...\CVS
...\...\...\...\...\Entries
...\...\...\...\...\Repository
...\...\...\...\...\Root
...\...\documentation
...\...\.............\CVS
...\...\.............\...\Entries
...\...\.............\...\Repository
...\...\.............\...\Root
...\...\rtl
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\verilog
...\...\...\.......\CVS
...\...\...\.......\...\Entries
...\...\...\.......\...\Repository
...\...\...\.......\...\Root
...\...\...\.......\i2c_master_bit_ctrl.v
...\...\...\.......\i2c_master_byte_ctrl.v
...\...\...\.......\i2c_master_defines.v
...\...\...\.......\i2c_master_top.v
...\...\...\.......\timescale.v
...\...\...\vhdl
...\...\...\....\CVS
...\...\...\....\...\Entries
...\...\...\....\...\Repository
...\...\...\....\...\Root
...\...\...\....\I2C.VHD
...\...\...\....\i2c_master_bit_ctrl.vhd
...\...\...\....\i2c_master_byte_ctrl.vhd
...\...\...\....\i2c_master_top.vhd
...\...\...\....\readme
...\...\...\....\tst_ds1621.vhd
...\...\sim
...\...\...\CVS
...\...\...\...\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\i2c_verilog
...\...\...\...........\CVS
...\...\...\...........\...\Entries
...\...\...\...........\...\Repository
...\...\...\...........\...\Root
...\...\...\...........\run
...\...\...\...........\...\bench.vcd
...\...\...\...........\...\CVS
...\...\...\...........\...\...\Entries
...\...\...\...........\...\...\Repository
...\...\...\...........\...\...\Root
...\...\...\...........\...\INCA_libs
...\...\...\...........\...\.........\CVS
...\...\...\...........\...\.........\...\Entries
...\...\...\...........\...\.........\...\Repository
...\...\...\...........\...\.........\...\Root
...\...\...\...........\...\ncverilog.key
...\...\...\...........\...\ncverilog.log
...\...\...\...........\...\run
...\...\...\...........\...\waves
...\...\...\...........\...\.....\CVS
...\...\...\...........\...\.....\...\Entries
...\...\...\...........\...\.....\...\Repository
...\...\...\...........\...\.....\...\Root
...\...\software
...\...\........\CVS
...\...\........\...\Entries
...\...\........\...\Repository
...\...\........\...\Root
...\...\........\drivers
...\...\........\.......\CVS
...\...\........\.......\...\Entries
...\...\........\.......\...\Repository