文件名称:chap10
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《Verilog HDL 程序设计教程》7-"Verilog HDL Design Guide," 7
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下载文件列表
chap10
......\acc.acf
......\acc.hif
......\acc.v
......\accn.v
......\add8.v
......\adder8.v
......\block1.v
......\block2.v
......\block3.v
......\block4.v
......\control.v
......\fsm.v
......\longframe1.v
......\longframe2.v
......\pipeline.v
......\reg8.v
......\resource1.v
......\resource2.v
......\acc.acf
......\acc.hif
......\acc.v
......\accn.v
......\add8.v
......\adder8.v
......\block1.v
......\block2.v
......\block3.v
......\block4.v
......\control.v
......\fsm.v
......\longframe1.v
......\longframe2.v
......\pipeline.v
......\reg8.v
......\resource1.v
......\resource2.v