文件名称:riscmcu
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精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
riscmcu
.......\accum.v
.......\accum.v.bak
.......\addr_decode.v
.......\addr_decode.v.bak
.......\adr.v
.......\adr.v.bak
.......\alu.v
.......\alu.v.bak
.......\clk_gen.v
.......\clk_gen.v.bak
.......\counter.v
.......\counter.v.bak
.......\datact1.v
.......\datact1.v.bak
.......\machine.v
.......\machine.v.bak
.......\machinect1.v
.......\machinect1.v.bak
.......\ram.v
.......\ram.v.bak
.......\register.v
.......\register.v.bak
.......\RISCCPU.doc
.......\riscmcu.cr.mti
.......\riscmcu.mpf
.......\riscmcu.v
.......\riscmcu.v.bak
.......\riscmcu.wlf
.......\rom.v
.......\rom.v.bak
.......\rom_data
.......\transcript
.......\vish_stacktrace.vstf
.......\vsim.wlf
.......\wave.do
.......\work
.......\....\accum
.......\....\.....\verilog.asm
.......\....\.....\_primary.dat
.......\....\.....\_primary.vhd
.......\....\addr_decode
.......\....\...........\verilog.asm
.......\....\...........\_primary.dat
.......\....\...........\_primary.vhd
.......\....\adr
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\alu
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\clk_gen
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\counter
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\datact1
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\machine
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\machinect1
.......\....\..........\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\ram
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\register
.......\....\........\verilog.asm
.......\....\........\_primary.dat
.......\....\........\_primary.vhd
.......\....\riscmcu
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\rom
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\_info
.......\accum.v
.......\accum.v.bak
.......\addr_decode.v
.......\addr_decode.v.bak
.......\adr.v
.......\adr.v.bak
.......\alu.v
.......\alu.v.bak
.......\clk_gen.v
.......\clk_gen.v.bak
.......\counter.v
.......\counter.v.bak
.......\datact1.v
.......\datact1.v.bak
.......\machine.v
.......\machine.v.bak
.......\machinect1.v
.......\machinect1.v.bak
.......\ram.v
.......\ram.v.bak
.......\register.v
.......\register.v.bak
.......\RISCCPU.doc
.......\riscmcu.cr.mti
.......\riscmcu.mpf
.......\riscmcu.v
.......\riscmcu.v.bak
.......\riscmcu.wlf
.......\rom.v
.......\rom.v.bak
.......\rom_data
.......\transcript
.......\vish_stacktrace.vstf
.......\vsim.wlf
.......\wave.do
.......\work
.......\....\accum
.......\....\.....\verilog.asm
.......\....\.....\_primary.dat
.......\....\.....\_primary.vhd
.......\....\addr_decode
.......\....\...........\verilog.asm
.......\....\...........\_primary.dat
.......\....\...........\_primary.vhd
.......\....\adr
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\alu
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\clk_gen
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\counter
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\datact1
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\machine
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\machinect1
.......\....\..........\verilog.asm
.......\....\..........\_primary.dat
.......\....\..........\_primary.vhd
.......\....\ram
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\register
.......\....\........\verilog.asm
.......\....\........\_primary.dat
.......\....\........\_primary.vhd
.......\....\riscmcu
.......\....\.......\verilog.asm
.......\....\.......\_primary.dat
.......\....\.......\_primary.vhd
.......\....\rom
.......\....\...\verilog.asm
.......\....\...\_primary.dat
.......\....\...\_primary.vhd
.......\....\_info