文件名称:adder_Xilinx_Spartan_3
- 所属分类:
- VHDL编程
- 资源属性:
- [ASM] [源码]
- 上传时间:
- 2012-11-26
- 文件大小:
- 78kb
- 下载次数:
- 0次
- 提 供 者:
- tangx******
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
介绍说明--下载内容均来自于网络,请自行研究使用
这是个基于 Xilinx Spartan3 的加法器,利用Verilog语言编写,对于EDA初学者来说有一定的参考价值。
-This is based on the Xilinx Spartan3 Adder, Verilog language use, EDA newcomer has some reference value.
-This is based on the Xilinx Spartan3 Adder, Verilog language use, EDA newcomer has some reference value.
相关搜索: spartan3
(系统自动生成,下载前可以参看下载内容)
下载文件列表
adder
.....\.untf
.....\adder.dhp
.....\adder.npl
.....\adder4.bld
.....\adder4.cmd_log
.....\adder4.ldo
.....\adder4.lfp
.....\adder4.lso
.....\adder4.mrp
.....\adder4.nc1
.....\adder4.ncd
.....\adder4.ngc
.....\adder4.ngd
.....\adder4.ngm
.....\adder4.ngr
.....\adder4.pad
.....\adder4.pad_txt
.....\adder4.par
.....\adder4.pcf
.....\adder4.placed_ncd_tracker
.....\adder4.prj
.....\adder4.routed_ncd_tracker
.....\adder4.spl
.....\adder4.stx
.....\adder4.sym
.....\adder4.syr
.....\adder4.twr
.....\adder4.twx
.....\adder4.ucf
.....\adder4.ucf.untf
.....\adder4.v
.....\adder4.xlate_nlf
.....\adder4.xpi
.....\adder4t.v
.....\adder4_adder4t_v_tf.fdo
.....\adder4_adder4t_v_tf.udo
.....\adder4_fpga_editor.log
.....\adder4_last_par.ncd
.....\adder4_map.ncd
.....\adder4_map.ngm
.....\adder4_map_fpga_editor.log
.....\adder4_pad.csv
.....\adder4_pad.txt
.....\adder4_translate.nlf
.....\adder4_translate.v
.....\adder4_vhdl.prj
.....\automake.log
.....\coregen.log
.....\coregen.prj
.....\transcript
.....\vish_stacktrace.vstf
.....\vsim.wlf
.....\work
.....\....\adder4
.....\....\......\verilog.asm
.....\....\......\_primary.dat
.....\....\......\_primary.vhd
.....\....\adder4_adder4t_v_tf
.....\....\...................\verilog.asm
.....\....\...................\_primary.dat
.....\....\...................\_primary.vhd
.....\....\glbl
.....\....\....\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\_info
.....\xst
.....\...\work
.....\...\....\hdllib.ref
.....\...\....\vlg58
.....\...\....\.....\adder4.bin
.....\_ngo
.....\....\netlist.lst
.....\__projnav
.....\.........\adder.gfl
.....\.........\adder4.xst
.....\.........\adder_flowplus.gfl
.....\.........\coregen.rsp
.....\.........\createTF.err
.....\.........\ednTOngd_tcl.rsp
.....\.........\jhdparse.log
.....\.........\map.log
.....\.........\mfea_tcl.rsp
.....\.........\nc1TOncd_tcl.rsp
.....\.........\par.log
.....\.........\parentEditConstraintsTextApp_tcl.rsp
.....\.........\parFloorPlanner.rsp
.....\.........\pfea_tcl.rsp
.....\.........\posttrc.log
.....\.........\runXst_tcl.rsp
.....\.........\xlateFloorPlanner.rsp
.....\__projnav.log
.....\.untf
.....\adder.dhp
.....\adder.npl
.....\adder4.bld
.....\adder4.cmd_log
.....\adder4.ldo
.....\adder4.lfp
.....\adder4.lso
.....\adder4.mrp
.....\adder4.nc1
.....\adder4.ncd
.....\adder4.ngc
.....\adder4.ngd
.....\adder4.ngm
.....\adder4.ngr
.....\adder4.pad
.....\adder4.pad_txt
.....\adder4.par
.....\adder4.pcf
.....\adder4.placed_ncd_tracker
.....\adder4.prj
.....\adder4.routed_ncd_tracker
.....\adder4.spl
.....\adder4.stx
.....\adder4.sym
.....\adder4.syr
.....\adder4.twr
.....\adder4.twx
.....\adder4.ucf
.....\adder4.ucf.untf
.....\adder4.v
.....\adder4.xlate_nlf
.....\adder4.xpi
.....\adder4t.v
.....\adder4_adder4t_v_tf.fdo
.....\adder4_adder4t_v_tf.udo
.....\adder4_fpga_editor.log
.....\adder4_last_par.ncd
.....\adder4_map.ncd
.....\adder4_map.ngm
.....\adder4_map_fpga_editor.log
.....\adder4_pad.csv
.....\adder4_pad.txt
.....\adder4_translate.nlf
.....\adder4_translate.v
.....\adder4_vhdl.prj
.....\automake.log
.....\coregen.log
.....\coregen.prj
.....\transcript
.....\vish_stacktrace.vstf
.....\vsim.wlf
.....\work
.....\....\adder4
.....\....\......\verilog.asm
.....\....\......\_primary.dat
.....\....\......\_primary.vhd
.....\....\adder4_adder4t_v_tf
.....\....\...................\verilog.asm
.....\....\...................\_primary.dat
.....\....\...................\_primary.vhd
.....\....\glbl
.....\....\....\verilog.asm
.....\....\....\_primary.dat
.....\....\....\_primary.vhd
.....\....\_info
.....\xst
.....\...\work
.....\...\....\hdllib.ref
.....\...\....\vlg58
.....\...\....\.....\adder4.bin
.....\_ngo
.....\....\netlist.lst
.....\__projnav
.....\.........\adder.gfl
.....\.........\adder4.xst
.....\.........\adder_flowplus.gfl
.....\.........\coregen.rsp
.....\.........\createTF.err
.....\.........\ednTOngd_tcl.rsp
.....\.........\jhdparse.log
.....\.........\map.log
.....\.........\mfea_tcl.rsp
.....\.........\nc1TOncd_tcl.rsp
.....\.........\par.log
.....\.........\parentEditConstraintsTextApp_tcl.rsp
.....\.........\parFloorPlanner.rsp
.....\.........\pfea_tcl.rsp
.....\.........\posttrc.log
.....\.........\runXst_tcl.rsp
.....\.........\xlateFloorPlanner.rsp
.....\__projnav.log